diff options
author | Stefan Roese <sr@denx.de> | 2017-04-24 18:45:21 +0300 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2017-05-09 14:38:18 +0300 |
commit | cb686454c74c20617a91276083c41b19f7d118ad (patch) | |
tree | cf52b5bca225923b12bbd65c2a166a96d4ce94a8 | |
parent | 18797ad6c377b3a253a4c6ddb457aa8239dfe591 (diff) | |
download | u-boot-cb686454c74c20617a91276083c41b19f7d118ad.tar.xz |
phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFI
Use correct naming as done in the latest Marvell U-Boot version as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
-rw-r--r-- | arch/arm/dts/armada-8040-db.dts | 8 | ||||
-rw-r--r-- | arch/arm/dts/armada-8040-mcbin.dts | 10 | ||||
-rw-r--r-- | drivers/phy/marvell/comphy_core.c | 2 | ||||
-rw-r--r-- | drivers/phy/marvell/comphy_cp110.c | 18 | ||||
-rw-r--r-- | include/dt-bindings/comphy/comphy_data.h | 2 |
5 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 1fcb9f4963..fa589956ad 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -113,7 +113,7 @@ /* Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: SATA0 - * Lane 2: KR (10G) + * Lane 2: SFI (10G) * Lane 3: SATA1 * Lane 4: USB3_HOST1 * Lane 5: PCIe2 (x1) @@ -125,7 +125,7 @@ phy-type = <PHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; }; phy3 { phy-type = <PHY_TYPE_SATA1>; @@ -205,7 +205,7 @@ /* Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: SATA0 - * Lane 2: KR (10G) + * Lane 2: SFI (10G) * Lane 3: SATA1 * Lane 4: PCIe1 (x1) * Lane 5: PCIe2 (x1) @@ -217,7 +217,7 @@ phy-type = <PHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; }; phy3 { phy-type = <PHY_TYPE_SATA1>; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index e42b092b25..dde495ae4f 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -99,7 +99,7 @@ * [54] 2.5G SFP LOS * [55] Micro SD card detect * [56-61] Micro SD - * [62] CP1 KR SFP FAULT + * [62] CP1 SFI SFP FAULT */ /* 0 1 2 3 4 5 6 7 8 9 */ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff @@ -163,7 +163,7 @@ * Lane 1: PCIe0 (x4) * Lane 2: PCIe0 (x4) * Lane 3: PCIe0 (x4) - * Lane 4: KR (10G) + * Lane 4: SFI (10G) * Lane 5: SATA1 */ phy0 { @@ -179,7 +179,7 @@ phy-type = <PHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; }; phy5 { phy-type = <PHY_TYPE_SATA1>; @@ -268,7 +268,7 @@ * Lane 1: SATA 0 * Lane 2: USB HOST 0 * Lane 3: SATA1 - * Lane 4: KR (10G) + * Lane 4: SFI (10G) * Lane 5: SGMII3 */ phy0 { @@ -285,7 +285,7 @@ phy-type = <PHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; }; phy5 { phy-type = <PHY_TYPE_SGMII3>; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 7729e4be66..97455c8296 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -37,7 +37,7 @@ static char *get_type_string(u32 type) "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "KR"}; + "RXAUI0", "RXAUI1", "SFI"}; if (type < 0 || type > PHY_TYPE_MAX) return "invalid"; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 25c067d23f..cd3cf968cf 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -34,7 +34,7 @@ struct utmi_phy_data { * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet * option has different options, for example: serdes lane2 had option - * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR) + * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ @@ -43,13 +43,13 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_XAUI1, 0x1}, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, @@ -907,8 +907,8 @@ static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, return ret; } -static int comphy_kr_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) +static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, + void __iomem *comphy_base) { u32 mask, data, ret = 1; void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); @@ -1696,9 +1696,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, lane, ptr_comphy_map->speed, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_KR: - ret = comphy_kr_power_up(lane, hpipe_base_addr, - comphy_base_addr); + case PHY_TYPE_SFI: + ret = comphy_sfi_power_up(lane, hpipe_base_addr, + comphy_base_addr); break; case PHY_TYPE_RXAUI0: case PHY_TYPE_RXAUI1: diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index a3a6b405eb..8fd578aeaf 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -42,7 +42,7 @@ #define PHY_TYPE_XAUI3 20 #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_KR 23 +#define PHY_TYPE_SFI 23 #define PHY_TYPE_MAX 24 #define PHY_TYPE_INVALID 0xff |