diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2022-01-28 11:11:33 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-02-08 19:00:03 +0300 |
| commit | 8257437d0f21c6edda161844052c0e05579af71b (patch) | |
| tree | 25ce300e845d7f6cb31c1ac35fc5baf376dd3758 | |
| parent | c1c1b345b1bd06328c9f16225ebbceb6f165bbb2 (diff) | |
| download | u-boot-8257437d0f21c6edda161844052c0e05579af71b.tar.xz | |
phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| -rw-r--r-- | drivers/phy/cadence/phy-cadence-sierra.c | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index eaa32939c1..0bc60bb73e 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -147,6 +147,13 @@ #define SIERRA_MAX_LANES 16 #define PLL_LOCK_TIME 100 +#define CDNS_SIERRA_INPUT_CLOCKS 3 +enum cdns_sierra_clock_input { + PHY_CLK, + CMN_REFCLK_DIG_DIV, + CMN_REFCLK1_DIG_DIV, +}; + static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); static const struct reg_field phy_pll_cfg_1 = @@ -204,9 +211,7 @@ struct cdns_sierra_phy { struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; - struct clk *clk; - struct clk *cmn_refclk; - struct clk *cmn_refclk1; + struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; int nsubnodes; u32 num_lanes; bool autoconf; @@ -257,8 +262,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) if (phy->autoconf) return 0; - clk_set_rate(phy->cmn_refclk, 25000000); - clk_set_rate(phy->cmn_refclk1, 25000000); + clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); + clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); if (ins->phy_type == PHY_TYPE_PCIE) { num_cmn_regs = phy->init_data->pcie_cmn_regs; @@ -459,7 +464,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, dev_err(dev, "failed to get clock phy_clk\n"); return PTR_ERR(clk); } - sp->clk = clk; + sp->input_clks[PHY_CLK] = clk; clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); if (IS_ERR(clk)) { @@ -467,7 +472,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, ret = PTR_ERR(clk); return ret; } - sp->cmn_refclk = clk; + sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); if (IS_ERR(clk)) { @@ -475,7 +480,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, ret = PTR_ERR(clk); return ret; } - sp->cmn_refclk1 = clk; + sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; return 0; } @@ -539,7 +544,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev) if (ret) return ret; - ret = clk_prepare_enable(sp->clk); + ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); if (ret) return ret; @@ -594,7 +599,7 @@ put_child: put_child2: clk_disable: - clk_disable_unprepare(sp->clk); + clk_disable_unprepare(sp->input_clks[PHY_CLK]); return ret; } |