arch: riscv: dts: dubhe: Update dts for Dubhe

Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>

2 files changed, 57 insertions, 25 deletions

diff --git a/arch/riscv/dts/dubhe.dtsi b/arch/riscv/dts/dubhe.dtsi
index 3ce659e1e7..5f3df5681c 100644
--- a/arch/riscv/dts/dubhe.dtsi
+++ b/arch/riscv/dts/dubhe.dtsi
@@ -12,21 +12,14 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
-			compatible = "starfive,dubhe0", "riscv";
-			d-cache-block-size = <64>;
-			d-cache-sets = <128>;
-			d-cache-size = <65536>;
+		cpu0: cpu@0 {
+			compatible = "starfive,dubhe", "riscv";
 			device_type = "cpu";
-			i-cache-block-size = <64>;
-			i-cache-sets = <512>;
-			i-cache-size = <65536>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <32>;
 			mmu-type = "riscv,sv48";
 			reg = <0x0>;
-			riscv,isa = "rv64imafdcbhnv";
+			riscv,isa = "rv64imafdcbh_sscofpmf";
 			tlb-split;
+
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -34,21 +27,14 @@
 			};
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "starfive,dubhe", "riscv";
-			d-cache-block-size = <64>;
-			d-cache-sets = <128>;
-			d-cache-size = <65536>;
 			device_type = "cpu";
-			i-cache-block-size = <64>;
-			i-cache-sets = <512>;
-			i-cache-size = <65536>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <32>;
 			mmu-type = "riscv,sv48";
 			reg = <0x1>;
-			riscv,isa = "rv64imafdcbhnv";
+			riscv,isa = "rv64imafdcbh_sscofpmf";
 			tlb-split;
+
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -61,6 +47,7 @@
 		#address-cells = <2>;
 		#size-cells = <2>;
 		compatible = "simple-bus";
+		dma-noncoherent;
 		ranges;
 
 		clint: clint@2000000 {
@@ -68,7 +55,9 @@
 			compatible = "riscv,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
 			interrupts-extended = <&cpu0_intc 3>,
-					      <&cpu0_intc 7>;
+					      <&cpu0_intc 7>,
+					      <&cpu1_intc 3>,
+					      <&cpu1_intc 7>;
 		};
 
 		pbus_clk: subsystem_pbus_clock {
@@ -86,7 +75,9 @@
 			riscv,ndev = <25>;
 			interrupt-controller;
 			interrupts-extended = <&cpu0_intc 11>,
-					      <&cpu0_intc 9>;
+					      <&cpu0_intc 9>,
+					      <&cpu1_intc 11>,
+					      <&cpu1_intc 9>;
 		};
 
 		spi0: spi@10000000 {
@@ -154,6 +145,47 @@
 			snps,txpbl = <4>;
 			snps,rxpbl = <4>;
 			status = "disabled";
-		};		
+		};
+
+		pmu {
+			compatible = "riscv,pmu";
+			interrupts-extended = <&cpu0_intc 13>,
+				<&cpu1_intc 13>;
+			riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
+				<0x00006 0x0000 0xB>,
+				<0x00008 0x0000 0x10>,
+				<0x00009 0x0000 0xF>,
+				<0x10000 0x0000 0x19>,
+				<0x10001 0x0000 0x1A>,
+				<0x10002 0x0000 0x1B>,
+				<0x10003 0x0000 0x1C>,
+				<0x10008 0x0000 0x8>,
+				<0x10009 0x0000 0x9>,
+				<0x1000C 0x0000 0x9E>,
+				<0x1000D 0x0000 0x9F>,
+				<0x10010 0x0000 0x1D>,
+				<0x10011 0x0000 0x1E>,
+				<0x10012 0x0000 0x1F>,
+				<0x10013 0x0000 0x20>,
+				<0x10014 0x0000 0x21>,
+				<0x10018 0x0000 0x17>,
+				<0x10019 0x0000 0x18>,
+				<0x10020 0x0000 0x8>,
+				<0x10021 0x0000 0x7>;
+
+			riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
+				<0x00008 0x00009 0x00007FF8>,
+				<0x10000 0x10003 0x00007FF8>,
+				<0x10008 0x10009 0x00007FF8>,
+				<0x1000C 0x1000D 0x00007FF8>,
+				<0x10010 0x10014 0x00007FF8>,
+				<0x10018 0x10019 0x00007FF8>,
+				<0x10020 0x10021 0x00007FF8>;
+
+			riscv,raw-event-to-mhpmcounters =
+				<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
+				<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
+				<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */
+		};
 	};
 };
diff --git a/arch/riscv/dts/dubhe_fpga.dts b/arch/riscv/dts/dubhe_fpga.dts
index d1accac57f..a98bb658f4 100644
--- a/arch/riscv/dts/dubhe_fpga.dts
+++ b/arch/riscv/dts/dubhe_fpga.dts
@@ -14,7 +14,7 @@
 	};
 
 	chosen {
-		bootargs = "console=ttySIF0,115200 earlycon=sbi root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
+		bootargs = "console=ttySIF0,115200 earlycon=sbi ip=:::255.255.255.0::eth0:dhcp";
 	};
 
 	cpus {