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| author | Shengyu Qu <wiagn233@outlook.com> | 2023-08-24 19:25:20 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-09-05 05:53:46 +0300 |
| commit | 64339bc1f2ae2c0bfcc058a5001284a9a222f15b (patch) | |
| tree | 3c02771ec8c30b559261d900b070d42f6e8fefa2 | |
| parent | c9db9a2ef5558dc1e83965e452030dbf5ce93de2 (diff) | |
| download | u-boot-64339bc1f2ae2c0bfcc058a5001284a9a222f15b.tar.xz | |
riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
would be triggered. Currently, we use DDR ram for SPL malloc arena on
Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
SPL malloc arena. To avoid triggering ECC error in this scenario, we
imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.
Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/jh7110/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5..e5549a01b8 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT |