diff options
author | Jonas Karlman <jonas@kwiboo.se> | 2023-03-14 03:38:27 +0300 |
---|---|---|
committer | Kever Yang <kever.yang@rock-chips.com> | 2023-03-19 08:17:28 +0300 |
commit | 67a1d773e7ed1bbfe05ff02d13e56558e7203af5 (patch) | |
tree | e9683d8a08801caa7b38680710683600656a59a5 | |
parent | a67e219d0ca1b4b45ddb0cfb0afa2d1781262f62 (diff) | |
download | u-boot-67a1d773e7ed1bbfe05ff02d13e56558e7203af5.tar.xz |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver
The rate and error value is not returned for aux16m clocks, fix this.
Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
-rw-r--r-- | drivers/clk/rockchip/clk_rk3588.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 5271d94348..a7df553e87 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_get_clk(priv, clk->id); + rate = rk3588_aux16m_get_clk(priv, clk->id); break; case ACLK_VOP_ROOT: case ACLK_VOP: @@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_set_clk(priv, clk->id, rate); + ret = rk3588_aux16m_set_clk(priv, clk->id, rate); break; case ACLK_VOP_ROOT: case ACLK_VOP: |