arch: riscv: dubhe: Update Dubhe support

Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>

7 files changed, 143 insertions, 111 deletions

diff --git a/arch/riscv/cpu/dubhe/Makefile b/arch/riscv/cpu/dubhe/Makefile
index a6886d6cdc..7304fe8a4b 100644
--- a/arch/riscv/cpu/dubhe/Makefile
+++ b/arch/riscv/cpu/dubhe/Makefile
@@ -4,3 +4,7 @@
 
 obj-y += dram.o
 obj-y += cpu.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += cache.o
+endif
\ No newline at end of file
diff --git a/arch/riscv/cpu/dubhe/cache.c b/arch/riscv/cpu/dubhe/cache.c
new file mode 100755
index 0000000000..e593fe537b
--- /dev/null
+++ b/arch/riscv/cpu/dubhe/cache.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
+
+#include <common.h>
+#include <asm/sbi.h>
+
+#define SBI_EXT_CACHE	0x09057485
+
+enum sbi_ext_cache_fid {
+	SBI_EXT_BASE_L2_FLUSH = 0,
+	SBI_EXT_BASE_L2_INVALIDATE,
+};
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	sbi_ecall(SBI_EXT_CACHE, SBI_EXT_BASE_L2_FLUSH, start, end - start, 0, 0, 0, 0);
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	sbi_ecall(SBI_EXT_CACHE, SBI_EXT_BASE_L2_INVALIDATE, start, end - start, 0, 0, 0, 0);
+}
diff --git a/arch/riscv/cpu/dubhe/dram.c b/arch/riscv/cpu/dubhe/dram.c
index e262ab811a..2f0b7eb0f2 100644
--- a/arch/riscv/cpu/dubhe/dram.c
+++ b/arch/riscv/cpu/dubhe/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
 	return fdtdec_setup_memory_banksize();
 }
 
-ulong board_get_usable_ram_top(ulong total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/*
 	 * Ensure that we run from first 4GB so that all
diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
index 72575fdc1c..97ba528f10 100755
--- a/drivers/ram/starfive/Kconfig
+++ b/drivers/ram/starfive/Kconfig
@@ -1,10 +1,9 @@
-<<<<<<< HEAD
 config SPL_STARFIVE_DDR
 	bool "StarFive DDR driver in SPL"
 	depends on SPL_RAM && STARFIVE_JH7110
 	help
 	  This enables DDR support for the platforms based on StarFive JH7110 SoC.
-=======
+
 config RAM_STARFIVE
 	bool "Ram drivers support for StarFive SoCs"
 	depends on RAM && RISCV
@@ -12,10 +11,9 @@ config RAM_STARFIVE
 	help
 	  This enables support for ram drivers of StarFive SoCs.
 
-config STARFIVE_DDR
-	bool "StarFive DDR driver"
+config STARFIVE_DUBHE_DDR
+	bool "StarFive Dubhe DDR driver"
 	depends on RAM_STARFIVE
 	default y if TARGET_STARFIVE_DUBHE_FPGA
 	help
-	  This enables DDR4/LPDDR4 support for the platforms based on StarFive SoC.
->>>>>>> Add DDR driver framework
+	  This enables DDR4/LPDDR4 support for the platforms based on StarFive Dubhe.
diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
index 22d8ffd3ab..015bb82f19 100755
--- a/drivers/ram/starfive/Makefile
+++ b/drivers/ram/starfive/Makefile
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
-<<<<<<< HEAD
 # Copyright (c) 2022 StarFive, Inc
 #
 ifdef CONFIG_SPL_BUILD
@@ -10,9 +9,5 @@ obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
 obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
 obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
 endif
-=======
-# Copyright (c) 2021 StarFive Technology Co., Ltd.
-#
 
-obj-$(CONFIG_STARFIVE_DDR) += starfive_ddr.o
->>>>>>> Add DDR driver framework
+obj-$(CONFIG_STARFIVE_DUBHE_DDR) += starfive_dubhe_ddr.o
diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c
index 23c6c05898..0fa317087a 100755
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
@@ -130,96 +129,11 @@ err_free_reset:
 	reset_release_bulk(&priv->rst);
 
 	return ret;
-=======
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (c) 2021 StarFive Technology Co., Ltd.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <init.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <clk.h>
-#include <wait_bit.h>
-#include <linux/bitops.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct starfive_ddrctl {
-	volatile u32 ctl_settings[1];
-};
-
-struct starfive_ddrphy {
-	volatile u32 phy_settings[1];
-};
-
-/**
- * struct starfive_ddr_info
- *
- * @dev: pointer for the device
- * @info: UCLASS RAM information
- * @clk: clock
- * @ctl: controller base address
- * @phy: PHY base address
- */
-struct starfive_ddr_info {
-	struct udevice *dev;
-	struct ram_info info;
-	struct clk clk;
-	struct starfive_ddrctl *ctl;
-	struct starfive_ddrphy *phy;
-};
-
-struct starfive_ddr_params {
-	struct starfive_ddrctl ctrl_regs;
-	struct starfive_ddrphy phy_regs;
-};
-
-struct starfive_ddr_plat {
-	struct starfive_ddr_params ddr_params;
-};
-
-static int starfive_ddr_probe(struct udevice *dev)
-{
-	struct starfive_ddr_info *priv = dev_get_priv(dev);
-#if defined(CONFIG_SPL_BUILD)
-	int ret;
-#endif
-
-	debug("starfive_ddr_probe\n");
-
-	/* Get memory base and size */
-	fdtdec_setup_mem_size_base();
-	priv->info.base = gd->ram_base;
-	priv->info.size = gd->ram_size;
-
-#if defined(CONFIG_SPL_BUILD)
-	debug("starfive_ddr_probe probing clock and setup ctl/phy settings\n");
-	priv->dev = dev;
-
-	ret = clk_get_by_index(dev, 0, &priv->clk);
-	if (ret) {
-		debug("clk_get_by_index error:%d\n", ret);
-		return ret;
-	}
-#endif
-
-	return 0;
->>>>>>> Add DDR driver framework
 }
 
 static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
 {
-<<<<<<< HEAD
 	struct starfive_ddr_priv *priv = dev_get_priv(dev);
-=======
-	struct starfive_ddr_info *priv = dev_get_priv(dev);
->>>>>>> Add DDR driver framework
 
 	*info = priv->info;
 
@@ -231,11 +145,7 @@ static struct ram_ops starfive_ddr_ops = {
 };
 
 static const struct udevice_id starfive_ddr_ids[] = {
-<<<<<<< HEAD
 	{ .compatible = "starfive,jh7110-dmc" },
-=======
-	{ .compatible = "starfive,dubhe-ddr" },
->>>>>>> Add DDR driver framework
 	{ }
 };
 
@@ -245,12 +155,5 @@ U_BOOT_DRIVER(starfive_ddr) = {
 	.of_match = starfive_ddr_ids,
 	.ops = &starfive_ddr_ops,
 	.probe = starfive_ddr_probe,
-<<<<<<< HEAD
 	.priv_auto = sizeof(struct starfive_ddr_priv),
-=======
-	.priv_auto = sizeof(struct starfive_ddr_info),
-#if defined(CONFIG_SPL_BUILD)
-	.plat_auto = sizeof(struct starfive_ddr_plat),
-#endif
->>>>>>> Add DDR driver framework
-};
+};
\ No newline at end of file
diff --git a/drivers/ram/starfive/starfive_dubhe_ddr.c b/drivers/ram/starfive/starfive_dubhe_ddr.c
new file mode 100755
index 0000000000..ed7fc3c68d
--- /dev/null
+++ b/drivers/ram/starfive/starfive_dubhe_ddr.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <wait_bit.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct starfive_ddrctl {
+	volatile u32 ctl_settings[1];
+};
+
+struct starfive_ddrphy {
+	volatile u32 phy_settings[1];
+};
+
+/**
+ * struct starfive_ddr_info
+ *
+ * @dev: pointer for the device
+ * @info: UCLASS RAM information
+ * @clk: clock
+ * @ctl: controller base address
+ * @phy: PHY base address
+ */
+struct starfive_ddr_info {
+	struct udevice *dev;
+	struct ram_info info;
+	struct clk clk;
+	struct starfive_ddrctl *ctl;
+	struct starfive_ddrphy *phy;
+};
+
+struct starfive_ddr_params {
+	struct starfive_ddrctl ctrl_regs;
+	struct starfive_ddrphy phy_regs;
+};
+
+struct starfive_ddr_plat {
+	struct starfive_ddr_params ddr_params;
+};
+
+static int starfive_ddr_probe(struct udevice *dev)
+{
+	struct starfive_ddr_info *priv = dev_get_priv(dev);
+#if defined(CONFIG_SPL_BUILD)
+	int ret;
+#endif
+
+	debug("starfive_ddr_probe\n");
+
+	/* Get memory base and size */
+	fdtdec_setup_mem_size_base();
+	priv->info.base = gd->ram_base;
+	priv->info.size = gd->ram_size;
+
+#if defined(CONFIG_SPL_BUILD)
+	debug("starfive_ddr_probe probing clock and setup ctl/phy settings\n");
+	priv->dev = dev;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret) {
+		debug("clk_get_by_index error:%d\n", ret);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+	struct starfive_ddr_info *priv = dev_get_priv(dev);
+
+	*info = priv->info;
+
+	return 0;
+}
+
+static struct ram_ops starfive_ddr_ops = {
+	.get_info = starfive_ddr_get_info,
+};
+
+static const struct udevice_id starfive_ddr_ids[] = {
+	{ .compatible = "starfive,dubhe-ddr" },
+	{ }
+};
+
+U_BOOT_DRIVER(starfive_ddr) = {
+	.name = "starfive_ddr",
+	.id = UCLASS_RAM,
+	.of_match = starfive_ddr_ids,
+	.ops = &starfive_ddr_ops,
+	.probe = starfive_ddr_probe,
+	.priv_auto = sizeof(struct starfive_ddr_info),
+#if defined(CONFIG_SPL_BUILD)
+	.plat_auto = sizeof(struct starfive_ddr_plat),
+#endif
+};