Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

- mvebu: Thecus: Misc enhancement and cleanup (Tony)
- mvebu: Add AC5X Allied Telesis x240 board support incl NAND
  controller enhancements for this SoC (Chris)

14 files changed, 514 insertions, 118 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6a40ac78f9..07b26df275 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -305,7 +305,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9132-db-B.dtb				\
 	cn9130-crb-A.dtb			\
 	cn9130-crb-B.dtb			\
-	ac5-98dx35xx-rd.dtb
+	ac5-98dx35xx-rd.dtb			\
+	ac5-98dx35xx-atl-x240.dtb
 endif
 
 dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
index 3c68355f32..f53b4781d7 100644
--- a/arch/arm/dts/ac5-98dx25xx.dtsi
+++ b/arch/arm/dts/ac5-98dx25xx.dtsi
@@ -251,6 +251,15 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@805b0000 {
+			compatible = "marvell,mvebu-ac5-pxa3xx-nand";
+			reg = <0x0 0x805b0000 0x0 0x54>;
+			#address-cells = <0x00000001>;
+			marvell,nand-enable-arbiter;
+			num-cs = <0x00000001>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@80600000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
diff --git a/arch/arm/dts/ac5-98dx35xx-atl-x240.dts b/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
new file mode 100644
index 0000000000..820ec18b43
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx35xx-atl-x240.dts
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "ac5-98dx35xx.dtsi"
+
+/ {
+	model = "Allied Telesis x240";
+	compatible = "alliedtelesis,x240", "marvell,ac5x", "marvell,ac5";
+
+	aliases {
+		serial0 = &uart0;
+		spiflash0 = &spiflash0;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		spi0 = &spi0;
+		i2c0 = &i2c0;
+		usb0 = &usb0;
+		pinctrl0 = &pinctrl0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	boot-board {
+		compatible = "atl,boot-board";
+		present-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		override-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		fault {
+			label = "fault:red";
+			gpios = <&system_gpio 11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+};
+
+&nand {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins>;
+
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@user {
+			reg = <0x00000000 0x10000000>;
+			label = "user";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	mux@71 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,pca9546";
+		reg = <0x71>;
+		i2c-mux-idle-disconnect;
+		reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;               /* MPP36 */
+		status = "okay";
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			hwmon@2e {
+				compatible = "adi,adt7476";
+				reg = <0x2e>;
+			};
+
+			rtc@68 {
+				compatible = "adi,max31331";
+				reg = <0x68>;
+			};
+
+			system_gpio: gpio@27 {
+				compatible = "nxp,pca9555";
+				gpio-controller;
+				#gpio-cells= <2>;
+				reg = <0x27>;
+				interrupt-parent = <&gpio0>;
+				interrupts = <25 IRQ_TYPE_LEVEL_LOW>;   /* MPP25 */
+			};
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+	spiflash0: flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&gpio0 {
+	phy-reset {
+		gpio-hog;
+		gpios = <19 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "phy-reset";
+	};
+
+	usb-en {
+		gpio-hog;
+		gpios = <28 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "usb-en";
+	};
+
+	led-oe-n {
+		gpio-hog;
+		gpios = <23 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "led-oe-n";
+	};
+};
+
+&gpio1 {
+	nand-protect {
+		gpio-hog;
+		gpios = <8 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "nand-protect";
+	};
+};
+
+&pinctrl0 {
+	/*
+	 * MPP Bus:              MPP#
+	 * NF_IO                 [0-7]
+	 * NF_Wen                [8]
+	 * NF_ALE                [9]
+	 * NF_CLE                [10]
+	 * NF_Cen                [11]
+	 * QSPI_SCK/SPI0_SCK     [12]
+	 * QSPI_CSn/SPI0_CSn     [13]
+	 * QSPI_DIO[0]/SPI0_MOSI [14]
+	 * QSPI_DIO[1]/SPI0_MISO [15]
+	 * NF_Ren                [16]
+	 * NF_RBn                [17]
+	 * WD_INTn               [18]
+	 * B_B_OVRIDE_N          [19]
+	 * GREEN_SW_N            [20]
+	 * PHY_INT_N[0]          [21]
+	 * SPI_WPn               [22]
+	 * LED_OE_N              [23]
+	 * USB_PWR_FLT_N         [24]
+	 * SFP_INT_N             [25]
+	 * I2C0_SCL              [26]
+	 * I2C0_SDA              [27]
+	 * USB_EN                [28]
+	 * MONITOR_INT_N         [29]
+	 * XM1_MDC               [30]
+	 * XM1_MDIO              [31]
+	 * UA0_RXD               [32]
+	 * UA0_TXD               [33]
+	 * PHY_RST0n             [34]
+	 * TPM_INT_N             [35]
+	 * I2CMUX_RESET_N        [36]
+	 * SPI_SRAM_SEL_N        [37]
+	 * B_B_PRESENT           [38]
+	 * SPI_FLASH_SEL_N       [39]
+	 * NF_WP_N               [40]
+	 * POE_INT_N             [41]
+	 * PoE_RST_N             [42]
+	 * LED0_CLK              [43]
+	 * LED0_STB              [44]
+	 * LED0_DATA             [45]
+	 */
+	/*	     0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 1    1    1    1    0xff 0xff 0    0
+		     0    0    0    0    0    0    1    1    0    0
+		     1    1    1    1    0    0    0    0    0    0
+		     0    0    0    1    1    1    >;
+
+	nand_pins: nand-pins {
+		marvell,pins = <0 1 2 3 4 5 6 7 8 9 10 11 16 17>;
+		marvell,function = <2>;
+	};
+};
diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
index d9f217cd4a..1dc85bb7ef 100644
--- a/arch/arm/dts/ac5-98dx35xx-rd.dts
+++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
@@ -31,7 +31,6 @@
 		usb0 = &usb0;
 		usb1 = &usb1;
 		pinctrl0 = &pinctrl0;
-		sar-reg0 = "/config-space/sar-reg";
 	};
 
 	usb1phy: usb-phy {
diff --git a/arch/arm/dts/armada-385-thecus-n2350.dts b/arch/arm/dts/armada-385-thecus-n2350.dts
index fc29c4d25a..253cf01130 100644
--- a/arch/arm/dts/armada-385-thecus-n2350.dts
+++ b/arch/arm/dts/armada-385-thecus-n2350.dts
@@ -23,7 +23,7 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
 		device_type = "memory";
 		reg = <0x00000000 0x40000000>; /* 1GB */
 	};
@@ -37,43 +37,43 @@
 
 	};
 
-	usb3_0_phy: usb3_0_phy {
+	usb3_0_phy: usb-phy {
 		compatible = "usb-nop-xceiv";
 		vcc-supply = <&usb3_0_power>;
+		 #phy-cells = <0>;
 	};
 
-	usb3_1_phy: usb3_1_phy {
+	usb3_1_phy: usb-phy {
 		compatible = "usb-nop-xceiv";
 		vcc-supply = <&usb3_1_power>;
+		 #phy-cells = <0>;
 	};
 
-	gpio-keys {
+	keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		pinctrl-0 = <&pmx_power_button &pmx_copy_button &pmx_reset_button>;
 		pinctrl-names = "default";
 
-		button@1 {
+		button-1 {
 			label = "Power Button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 		};
 
-		button@2 {
+		button-2 {
 			label = "Copy Button";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
 		};
 
-		button@3 {
+		button-3 {
 			label = "Reset Button";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	gpio-leds {
+	leds {
 		compatible = "gpio-leds";
 		pinctrl-0 = <&pmx_sata1_white_led
 				&pmx_sata1_red_led
@@ -88,142 +88,142 @@
 
 		pinctrl-names = "default";
 
-		white_sata1 {
+		led-1 {
 			label = "n2350:white:sata1";
 			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "ide-disk1";
 		};
 
-		red_sata1 {
+		led-2 {
 			label = "n2350:red:sata1";
 			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 		};
 
-		white-sata2 {
+		led-3 {
 			label = "n2350:white:sata2";
 			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
 		};
 
-		red-sata2 {
+		led-4 {
 			label = "n2350:red:sata2";
 			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 		};
 
-		white-sys {
+		led-5 {
 			label = "n2350:white:sys";
 			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "default-on";
 		};
 
-		red-sys {
+		led-6 {
 			label = "n2350:red:sys";
 			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
 		};
 
-		blue-pwr {
+		led-7 {
 			label = "n2350:blue:pwr";
 			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 		};
 
-		red-pwr {
+		led-8 {
 			label = "n2350:red:pwr";
 			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
 		};
 
-		white-usb {
+		led-9 {
 			label = "n2350:white:usb";
 			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
 		};
 
-		red-usb {
+		led-10 {
 			label = "n2350:red:usb";
 			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		usb3_0_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB3_0_Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
-		};
+	fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <	  0  0
+					600  1
+					3000 2 >;
+		pinctrl-0 = <&pmx_fan>;
+		pinctrl-names = "default";
+	};
 
-		usb3_1_power: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB3_1_Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
-		};
+	usb3_0_power: v5-vbus0 {
+		compatible = "regulator-fixed";
+		regulator-name = "USB3_0_Power";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_sata0: regulator@3 {
-			compatible = "regulator-fixed";
-			regulator-name = "pwr_en_sata0";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-		};
+	usb3_1_power: v5-vbus1 {
+		compatible = "regulator-fixed";
+		regulator-name = "USB3_1_Power";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_5v_sata0: v5-sata0 {
-			compatible = "regulator-fixed";
-			regulator-name = "v5.0-sata0";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			vin-supply = <&reg_sata0>;
-		};
+	reg_sata0: pwr-sata0 {
+		compatible = "regulator-fixed";
+		regulator-name = "pwr_en_sata0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_12v_sata0: v12-sata0 {
-			compatible = "regulator-fixed";
-			regulator-name = "v12.0-sata0";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			vin-supply = <&reg_sata0>;
-		};
+	reg_5v_sata0: v5-sata0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-sata0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_sata0>;
+	};
 
-		reg_sata1: regulator@4 {
-			regulator-name = "pwr_en_sata1";
-			compatible = "regulator-fixed";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
-		};
+	reg_12v_sata0: v12-sata0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v12.0-sata0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&reg_sata0>;
+	};
 
-		reg_5v_sata1: v5-sata1 {
-			compatible = "regulator-fixed";
-			regulator-name = "v5.0-sata1";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			vin-supply = <&reg_sata1>;
-		};
+	reg_sata1: pwr-sata0 {
+		regulator-name = "pwr_en_sata1";
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	};
 
-		reg_12v_sata1: v12-sata1 {
-			compatible = "regulator-fixed";
-			regulator-name = "v12.0-sata1";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			vin-supply = <&reg_sata1>;
-		};
+	reg_5v_sata1: v5-sata1 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-sata1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_sata1>;
+	};
 
+	reg_12v_sata1: v12-sata1 {
+		compatible = "regulator-fixed";
+		regulator-name = "v12.0-sata1";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&reg_sata1>;
 	};
 
 	gpio-poweroff {
@@ -267,7 +267,7 @@
 };
 
 &mdio {
-	phy0: ethernet-phy@0 {
+	phy0: ethernet-phy@1 {
 		reg = <1>;
 	};
 };
@@ -301,18 +301,14 @@
 
 &pciec {
 	status = "okay";
-	/*
-	 * The two PCIe units are accessible through
-	 * standard PCIe slots on the board.
-	 */
-	pcie@1,0 {
-		/* Port 0, Lane 0 */
-		status = "okay";
-	};
-	pcie@2,0 {
-		/* Port 1, Lane 0 */
-		status = "okay";
-	};
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
 };
 
 &pinctrl {
@@ -392,6 +388,11 @@
 		marvell,pins = "mpp17";
 		marvell,function = "gpio";
 	};
+
+	pmx_fan: pmx-fan {
+		marvell,pins = "mpp48";
+		marvell,function = "gpio";
+	};
 };
 
 &sdhci {
@@ -408,10 +409,10 @@
 	status = "okay";
 
 	/* spi: 4M Flash Macronix MX25L3205D */
-	spi-flash@0 {
+	flash@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "macronix,mx25l3205d", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		reg = <0>;
 
 		spi-max-frequency = <108000000>;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index ac484c73f6..5c7f4bf964 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -202,6 +202,10 @@ config TARGET_X530
 	bool "Support Allied Telesis x530"
 	select 88F6820
 
+config TARGET_X240
+	bool "Support Allied Telesis x240"
+	select ALLEYCAT_5
+
 config TARGET_DB_XC3_24G4XG
 	bool "Support DB-XC3-24G4XG"
 	select 98DX3336
@@ -274,6 +278,7 @@ config SYS_BOARD
 	default "theadorable" if TARGET_THEADORABLE
 	default "a38x" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "x240" if TARGET_X240
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
 	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
@@ -297,6 +302,7 @@ config SYS_CONFIG_NAME
 	default "turris_mox" if TARGET_TURRIS_MOX
 	default "controlcenterdc" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "x240" if TARGET_X240
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
 	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
@@ -320,6 +326,7 @@ config SYS_VENDOR
 	default "CZ.NIC" if TARGET_TURRIS_MOX
 	default "gdsys" if TARGET_CONTROLCENTERDC
 	default "alliedtelesis" if TARGET_X530
+	default "alliedtelesis" if TARGET_X240
 	default "mikrotik" if TARGET_CRS3XX_98DX3236
 	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
 
diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c
index dc69f46eed..734b0a87dd 100644
--- a/arch/arm/mach-mvebu/alleycat5/soc.c
+++ b/arch/arm/mach-mvebu/alleycat5/soc.c
@@ -255,6 +255,12 @@ void soc_print_clock_info(void)
 	printf("\tMSS     %4d MHz\n", 200);
 }
 
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void)
+{
+	return 400 * 1000000;
+}
+
 /*
  * Override of __weak int mach_cpu_init(void) :
  * SoC/machine dependent CPU setup
diff --git a/board/alliedtelesis/x240/MAINTAINERS b/board/alliedtelesis/x240/MAINTAINERS
new file mode 100644
index 0000000000..f1f78d9616
--- /dev/null
+++ b/board/alliedtelesis/x240/MAINTAINERS
@@ -0,0 +1,7 @@
+X240 BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/x240/
+F:	arch/arm/dts/ac5-98dx35xx-rd.dts
+F:	include/configs/x240.h
+F:	configs/x240_defconfig
diff --git a/board/alliedtelesis/x240/Makefile b/board/alliedtelesis/x240/Makefile
new file mode 100644
index 0000000000..7f20a47d6a
--- /dev/null
+++ b/board/alliedtelesis/x240/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 Allied Telesis
+#
+
+obj-y	+= x240.o
diff --git a/board/alliedtelesis/x240/x240.c b/board/alliedtelesis/x240/x240.c
new file mode 100644
index 0000000000..0c4f8e03b8
--- /dev/null
+++ b/board/alliedtelesis/x240/x240.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
diff --git a/board/thecus/n2350/n2350.c b/board/thecus/n2350/n2350.c
index fd8f95f944..05b125fd7f 100644
--- a/board/thecus/n2350/n2350.c
+++ b/board/thecus/n2350/n2350.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define N2350_GPP_OUT_ENA_LOW	(~(BIT(20) | BIT(21) | BIT(24)))
 #define N2350_GPP_OUT_ENA_MID	(~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
 #define N2350_GPP_OUT_VAL_LOW	(BIT(21) | BIT(24))
-#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13))
+#define N2350_GPP_OUT_VAL_MID	(BIT(0) | BIT(12) | BIT(13) | BIT(16))
 #define N2350_GPP_POL_LOW	0x0
 #define N2350_GPP_POL_MID	0x0
 
diff --git a/configs/x240_defconfig b/configs/x240_defconfig
new file mode 100644
index 0000000000..6d25c5ae3f
--- /dev/null
+++ b/configs/x240_defconfig
@@ -0,0 +1,86 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x200000000
+CONFIG_SYS_MALLOC_LEN=0x900000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
+CONFIG_TARGET_X240=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x00f80000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="ac5-98dx35xx-atl-x240"
+CONFIG_SYS_LOAD_ADDR=0x220000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MAX313XX=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+# CONFIG_FAT_WRITE is not set
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c
index fcd1b9c636..d502e967f9 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -125,6 +125,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* System control register and bit to enable NAND on some SoCs */
 #define GENCONF_SOC_DEVICE_MUX	0x208
 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
+#define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27)
 
 /*
  * This should be large enough to read 'ONFI' and 'JEDEC'.
@@ -167,6 +168,7 @@ enum pxa3xx_nand_variant {
 	PXA3XX_NAND_VARIANT_PXA,
 	PXA3XX_NAND_VARIANT_ARMADA370,
 	PXA3XX_NAND_VARIANT_ARMADA_8K,
+	PXA3XX_NAND_VARIANT_AC5,
 };
 
 struct pxa3xx_nand_host {
@@ -391,6 +393,10 @@ static const struct udevice_id pxa3xx_nand_dt_ids[] = {
 		.compatible = "marvell,armada-8k-nand-controller",
 		.data = PXA3XX_NAND_VARIANT_ARMADA_8K,
 	},
+	{
+		.compatible = "marvell,mvebu-ac5-pxa3xx-nand",
+		.data = PXA3XX_NAND_VARIANT_AC5,
+	},
 	{}
 };
 
@@ -505,6 +511,9 @@ static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
 		if (mode < 0)
 			mode = 0;
 
+		if (info->variant == PXA3XX_NAND_VARIANT_AC5)
+			mode = min(mode, 3);
+
 		timings = onfi_async_timing_mode_to_sdr_timings(mode);
 		if (IS_ERR(timings))
 			return PTR_ERR(timings);
@@ -730,7 +739,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
 
 		/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
 		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
-			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
+			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
+			info->variant == PXA3XX_NAND_VARIANT_AC5)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}
 
@@ -1579,7 +1589,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
 
 	/* Device detection must be done with ECC disabled */
 	if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
-		info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
+		info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
+		info->variant == PXA3XX_NAND_VARIANT_AC5)
 		nand_writel(info, NDECCCTRL, 0x0);
 
 	if (nand_scan_ident(mtd, 1, NULL))
@@ -1630,7 +1641,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
 	 */
 	if (mtd->writesize > info->chunk_size) {
 		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
-			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
+			info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
+			info->variant == PXA3XX_NAND_VARIANT_AC5) {
 			chip->cmdfunc = nand_cmdfunc_extended;
 		} else {
 			dev_err(mtd->dev,
@@ -1728,7 +1740,7 @@ static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *inf
 			return PTR_ERR(sysctrl_base);
 
 		regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
-		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
+		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN | GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN;
 		regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
 	}
 
diff --git a/include/configs/x240.h b/include/configs/x240.h
new file mode 100644
index 0000000000..3601df588d
--- /dev/null
+++ b/include/configs/x240.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Allied Telesis
+ */
+
+#ifndef __X240_H_
+#define __X240_H_
+
+#include <asm/arch/soc.h>
+
+/* additions for new ARM relocation support */
+#define CFG_SYS_SDRAM_BASE   0x200000000
+
+#define CFG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
+				      115200, 230400, 460800, 921600 }
+
+/* Default Env vars */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CFG_EXTRA_ENV_SETTINGS   \
+	BOOTENV \
+	"kernel_addr_r=0x202000000\0" \
+	"fdt_addr_r=0x201000000\0"    \
+	"ramdisk_addr_r=0x206000000\0"    \
+	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CFG_SYS_TCLK     325000000
+
+#endif /* __X240_H_ */