Add DDR driver framework

Reassign address for SPL STACK to avoid global data being wiped off during mem_malloc_init
Remove unused config CONFIG_SPL_LOAD_FIT_ADDRESS
Signed-off-by: woonjiet.chong <woonjiet.chong@starfivetech.com>

8 files changed, 146 insertions, 4 deletions

diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
index 39f452d48c..deadbee6a2 100644
--- a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
+++ b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
@@ -23,6 +23,15 @@
 
 	soc {
 		u-boot,dm-spl;
+		dmc: dmc@10280000 {
+			compatible = "starfive,dubhe-ddr";
+			reg = <0x0 0x10280000 0x0 0x10000
+			       0x0 0x10290000 0x0 0x10000
+			       0x0 0x102A0000 0x0 0x10000>;
+			clocks = <&pbus_clk>;
+			clock-frequency = <25000000>;
+			u-boot,dm-spl;
+		};
 	};
 };
 
diff --git a/board/starfive/dubhe_fpga/dubhe_fpga_spl.c b/board/starfive/dubhe_fpga/dubhe_fpga_spl.c
index d7a745e8c7..53e7c6b33e 100755
--- a/board/starfive/dubhe_fpga/dubhe_fpga_spl.c
+++ b/board/starfive/dubhe_fpga/dubhe_fpga_spl.c
@@ -1,10 +1,21 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
 
+#include <dm.h>
 #include <spl.h>
 
 int spl_board_init_f(void)
 {
+	int ret;
+	struct udevice *dev;
+
+	/* Init DRAM */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
 	return 0;
 }
 
diff --git a/configs/starfive_dubhe_fpga_defconfig b/configs/starfive_dubhe_fpga_defconfig
index a7163d9a15..4550f0a378 100644
--- a/configs/starfive_dubhe_fpga_defconfig
+++ b/configs/starfive_dubhe_fpga_defconfig
@@ -11,7 +11,6 @@ CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 # CONFIG_SPL_SMP is not set
 CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttySIF0,115200 earlycon=sbi root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
 CONFIG_USE_BOOTCOMMAND=y
@@ -35,5 +34,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
 CONFIG_SPI=y
 CONFIG_SPI_SIFIVE=y
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 6eb1a24135..593d2852f4 100644..100755
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_ARCH_OCTEON) += octeon/
 
 obj-$(CONFIG_ARCH_RMOBILE) += renesas/
 obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
+obj-$(CONFIG_RAM_STARFIVE) += starfive/
diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
index 80c790066f..72575fdc1c 100644..100755
--- a/drivers/ram/starfive/Kconfig
+++ b/drivers/ram/starfive/Kconfig
@@ -1,5 +1,21 @@
+<<<<<<< HEAD
 config SPL_STARFIVE_DDR
 	bool "StarFive DDR driver in SPL"
 	depends on SPL_RAM && STARFIVE_JH7110
 	help
 	  This enables DDR support for the platforms based on StarFive JH7110 SoC.
+=======
+config RAM_STARFIVE
+	bool "Ram drivers support for StarFive SoCs"
+	depends on RAM && RISCV
+	default y
+	help
+	  This enables support for ram drivers of StarFive SoCs.
+
+config STARFIVE_DDR
+	bool "StarFive DDR driver"
+	depends on RAM_STARFIVE
+	default y if TARGET_STARFIVE_DUBHE_FPGA
+	help
+	  This enables DDR4/LPDDR4 support for the platforms based on StarFive SoC.
+>>>>>>> Add DDR driver framework
diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
index 1df42c377b..22d8ffd3ab 100644..100755
--- a/drivers/ram/starfive/Makefile
+++ b/drivers/ram/starfive/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
+<<<<<<< HEAD
 # Copyright (c) 2022 StarFive, Inc
 #
 ifdef CONFIG_SPL_BUILD
@@ -8,4 +9,10 @@ obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
 obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
 obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
 obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
-endif
\ No newline at end of file
+endif
+=======
+# Copyright (c) 2021 StarFive Technology Co., Ltd.
+#
+
+obj-$(CONFIG_STARFIVE_DDR) += starfive_ddr.o
+>>>>>>> Add DDR driver framework
diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c
index a0a3d6b33d..23c6c05898 100644..100755
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
@@ -129,11 +130,96 @@ err_free_reset:
 	reset_release_bulk(&priv->rst);
 
 	return ret;
+=======
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <wait_bit.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct starfive_ddrctl {
+	volatile u32 ctl_settings[1];
+};
+
+struct starfive_ddrphy {
+	volatile u32 phy_settings[1];
+};
+
+/**
+ * struct starfive_ddr_info
+ *
+ * @dev: pointer for the device
+ * @info: UCLASS RAM information
+ * @clk: clock
+ * @ctl: controller base address
+ * @phy: PHY base address
+ */
+struct starfive_ddr_info {
+	struct udevice *dev;
+	struct ram_info info;
+	struct clk clk;
+	struct starfive_ddrctl *ctl;
+	struct starfive_ddrphy *phy;
+};
+
+struct starfive_ddr_params {
+	struct starfive_ddrctl ctrl_regs;
+	struct starfive_ddrphy phy_regs;
+};
+
+struct starfive_ddr_plat {
+	struct starfive_ddr_params ddr_params;
+};
+
+static int starfive_ddr_probe(struct udevice *dev)
+{
+	struct starfive_ddr_info *priv = dev_get_priv(dev);
+#if defined(CONFIG_SPL_BUILD)
+	int ret;
+#endif
+
+	debug("starfive_ddr_probe\n");
+
+	/* Get memory base and size */
+	fdtdec_setup_mem_size_base();
+	priv->info.base = gd->ram_base;
+	priv->info.size = gd->ram_size;
+
+#if defined(CONFIG_SPL_BUILD)
+	debug("starfive_ddr_probe probing clock and setup ctl/phy settings\n");
+	priv->dev = dev;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret) {
+		debug("clk_get_by_index error:%d\n", ret);
+		return ret;
+	}
+#endif
+
+	return 0;
+>>>>>>> Add DDR driver framework
 }
 
 static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
 {
+<<<<<<< HEAD
 	struct starfive_ddr_priv *priv = dev_get_priv(dev);
+=======
+	struct starfive_ddr_info *priv = dev_get_priv(dev);
+>>>>>>> Add DDR driver framework
 
 	*info = priv->info;
 
@@ -145,7 +231,11 @@ static struct ram_ops starfive_ddr_ops = {
 };
 
 static const struct udevice_id starfive_ddr_ids[] = {
+<<<<<<< HEAD
 	{ .compatible = "starfive,jh7110-dmc" },
+=======
+	{ .compatible = "starfive,dubhe-ddr" },
+>>>>>>> Add DDR driver framework
 	{ }
 };
 
@@ -155,5 +245,12 @@ U_BOOT_DRIVER(starfive_ddr) = {
 	.of_match = starfive_ddr_ids,
 	.ops = &starfive_ddr_ops,
 	.probe = starfive_ddr_probe,
+<<<<<<< HEAD
 	.priv_auto = sizeof(struct starfive_ddr_priv),
+=======
+	.priv_auto = sizeof(struct starfive_ddr_info),
+#if defined(CONFIG_SPL_BUILD)
+	.plat_auto = sizeof(struct starfive_ddr_plat),
+#endif
+>>>>>>> Add DDR driver framework
 };
diff --git a/include/configs/starfive-dubhe-fpga.h b/include/configs/starfive-dubhe-fpga.h
index 47957949b1..86e94ba2fc 100644
--- a/include/configs/starfive-dubhe-fpga.h
+++ b/include/configs/starfive-dubhe-fpga.h
@@ -6,10 +6,10 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
 #define CONFIG_SYS_SPL_MALLOC_START	0x80400000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
-#define CONFIG_SPL_STACK		0x80500000
+#define CONFIG_SPL_STACK		0x80600000
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR		0x80500000
+#define CONFIG_SYS_INIT_SP_ADDR		0x80600000
 #define CONFIG_SYS_LOAD_ADDR		0x84000000
 #define CONFIG_SYS_MALLOC_LEN		0x00100000
 #define CONFIG_SYS_BOOTM_LEN		0x04000000