diff options
| author | Wei Liang Lim <weiliang.lim@starfivetech.com> | 2023-10-21 18:32:38 +0300 |
|---|---|---|
| committer | Wei Liang Lim <weiliang.lim@starfivetech.com> | 2023-10-21 18:32:38 +0300 |
| commit | e12dda2ec6d0435c652634ef076b4f51e91c676b (patch) | |
| tree | 89dfc7cf3ab695b6530efd8b3aec714d195a8534 | |
| parent | ea34117e3e60c7ab65543f9ad9e0eb3e248f5ccd (diff) | |
| download | u-boot-e12dda2ec6d0435c652634ef076b4f51e91c676b.tar.xz | |
arch: riscv: dts: dubhe-fpga-u-boot.dtsi: Update dts for Dubhe
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
| -rw-r--r-- | arch/riscv/dts/dubhe-fpga-u-boot.dtsi | 42 |
1 files changed, 28 insertions, 14 deletions
diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi index 50f4f31ddf..bc853c54f5 100644 --- a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi +++ b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi @@ -4,29 +4,31 @@ / { chosen { stdout-path = "serial0"; + bootph-pre-ram; }; config { u-boot,spl-payload-offset = <0x42000>; + bootph-pre-ram; }; cpus { - bootph-all; + bootph-pre-ram; cpu@0 { - bootph-all; + bootph-pre-ram; }; cpu@1 { - bootph-all; + bootph-pre-ram; }; }; memory@80000000 { - bootph-all; + bootph-pre-ram; }; soc { - bootph-all; + bootph-pre-ram; dmc: dmc@10280000 { compatible = "starfive,dubhe-ddr"; reg = <0x0 0x10280000 0x0 0x10000 @@ -34,40 +36,52 @@ 0x0 0x102A0000 0x0 0x10000>; clocks = <&pbus_clk>; clock-frequency = <25000000>; - bootph-all; + bootph-pre-ram; }; }; }; +&clint { + bootph-pre-ram; +}; + +&pbus_clk { + bootph-pre-ram; +}; + +&plic0 { + bootph-pre-ram; +}; + &spi0 { - bootph-all; + bootph-pre-ram; mmc@0 { - bootph-all; + bootph-pre-ram; }; }; &qspi1 { - bootph-all; + bootph-pre-ram; flash@0 { - bootph-all; + bootph-pre-ram; }; }; &uart0 { - bootph-all; + bootph-pre-ram; }; &pbus_clk { - bootph-all; + bootph-pre-ram; }; &clint { clocks = <&pbus_clk>; - bootph-all; + bootph-pre-ram; }; &cpu0_intc { - bootph-all; + bootph-pre-ram; }; |