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author | Tom Rini <trini@konsulko.com> | 2023-09-05 16:04:49 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2023-09-05 16:04:49 +0300 |
commit | e7b7dca28f57e9331388550597c0687d3bfaded0 (patch) | |
tree | dba6f74cca2f0eb5726d838795b08fe87c7276bd | |
parent | 493fd3363f6da6a784514657d689c7cda0f390d5 (diff) | |
parent | dfe08374943c0e898fcfaf7327f69e0fb56b7d23 (diff) | |
download | u-boot-e7b7dca28f57e9331388550597c0687d3bfaded0.tar.xz |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ Implement OpenSBI DBCN extension for early debug console
+ Fixes for VisionFive2 board
+ Fix timer missing
+ Fix L2 LIM issue
+ Enable PCIE auto enumeration to support USB and NVMe by default
+ Set eth0 mac address properly
+ Add __noreturn attribute to spl_invoke_opensbi
-rw-r--r-- | Kconfig | 11 | ||||
-rw-r--r-- | arch/riscv/cpu/jh7110/Kconfig | 1 | ||||
-rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 9 | ||||
-rw-r--r-- | arch/riscv/include/asm/sbi.h | 1 | ||||
-rw-r--r-- | arch/riscv/lib/sbi.c | 16 | ||||
-rw-r--r-- | board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 2 | ||||
-rw-r--r-- | common/dlmalloc.c | 6 | ||||
-rw-r--r-- | common/spl/spl_opensbi.c | 7 | ||||
-rw-r--r-- | configs/starfive_visionfive2_defconfig | 10 | ||||
-rw-r--r-- | doc/board/starfive/visionfive2.rst | 2 | ||||
-rw-r--r-- | drivers/serial/Kconfig | 5 | ||||
-rw-r--r-- | drivers/serial/serial_sbi.c | 20 | ||||
-rw-r--r-- | drivers/timer/riscv_timer.c | 28 | ||||
-rw-r--r-- | include/spl.h | 2 |
14 files changed, 108 insertions, 12 deletions
@@ -372,6 +372,17 @@ if EXPERT When disabling this, please check if malloc calls, maybe should be replaced by calloc - if one expects zeroed memory. +config SPL_SYS_MALLOC_CLEAR_ON_INIT + bool "Init with zeros the memory reserved for malloc (slow) in SPL" + depends on SPL + default SYS_MALLOC_CLEAR_ON_INIT + help + Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to + Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards + that must have particular memory regions zero'ed before first use. + If SYS_SPL_MALLOC_START is configured to be in such region, this + option should be enabled. + config SYS_MALLOC_DEFAULT_TO_INIT bool "Default malloc to init while reserving the memory for it" help diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5..e5549a01b8 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 081b833331..ec237a46ff 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -163,6 +163,15 @@ }; }; + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc"; diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 009a26885c..bf4c9af622 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -170,5 +170,6 @@ int sbi_get_mvendorid(long *mvendorid); int sbi_get_marchid(long *marchid); int sbi_get_mimpid(long *mimpid); void sbi_srst_reset(unsigned long type, unsigned long reason); +int sbi_dbcn_write_byte(unsigned char ch); #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 8724e3a460..55a3bc3b5c 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -204,6 +204,22 @@ void sbi_srst_reset(unsigned long type, unsigned long reason) 0, 0, 0, 0); } +/** + * sbi_dbcn_write_byte() - write byte to debug console + * + * @ch: byte to be written + * Return: SBI error code (SBI_SUCCESS = 0 on success) + */ +int sbi_dbcn_write_byte(unsigned char ch) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_DBCN, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, + ch, 0, 0, 0, 0, 0); + return ret.error; +} + #ifdef CONFIG_SBI_V01 /** diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index befe7888c4..c334d98cf6 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -504,7 +504,7 @@ int mac_read_from_eeprom(void) } // 1, setup ethaddr env - eth_env_set_enetaddr("eth0addr", pbuf.eeprom.atom4.data.mac0_addr); + eth_env_set_enetaddr("ethaddr", pbuf.eeprom.atom4.data.mac0_addr); eth_env_set_enetaddr("eth1addr", pbuf.eeprom.atom4.data.mac1_addr); /** diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 0f9b7262d5..dcecdb8623 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -631,7 +631,7 @@ void mem_malloc_init(ulong start, ulong size) debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start, mem_malloc_end); -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) memset((void *)mem_malloc_start, 0x0, size); #endif malloc_bin_reloc(); @@ -2153,7 +2153,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; /* check if expand_top called, in which case don't need to clear */ -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) #if MORECORE_CLEARS mchunkptr oldtop = top; INTERNAL_SIZE_T oldtopsize = chunksize(top); @@ -2184,7 +2184,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; csz = chunksize(p); -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) #if MORECORE_CLEARS if (p == oldtop && csz > oldtopsize) { diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index b0f40076c3..e2aaa46046 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -43,11 +43,12 @@ static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node) return -ENODEV; } -void spl_invoke_opensbi(struct spl_image_info *spl_image) +void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image) { int ret, uboot_node; ulong uboot_entry; - void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info); + typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb, ulong info); + opensbi_entry_t opensbi_entry; if (!spl_image->fdt_addr) { pr_err("No device tree specified in SPL image\n"); @@ -74,7 +75,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS; opensbi_info.boot_hart = gd->arch.boot_hart; - opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; + opensbi_entry = (opensbi_entry_t)spl_image->entry_point; invalidate_icache_all(); #ifdef CONFIG_SPL_SMP diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index e9b63e5b84..9df6fcee0f 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_SYS_PCI_64BIT=y CONFIG_PCI=y +CONFIG_PCI_INIT_R=y CONFIG_TARGET_STARFIVE_VISIONFIVE2=y CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000 CONFIG_ARCH_RV64I=y @@ -43,7 +44,7 @@ CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};" +CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y @@ -58,6 +59,8 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_SYS_MALLOC_CLEAR_ON_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 CONFIG_SPL_I2C=y @@ -124,4 +127,9 @@ CONFIG_TIMER_EARLY=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_PCI=y +CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 941899a0a4..460f23aec3 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -20,6 +20,8 @@ The support for following drivers are already enabled: 3. StarFive JH7110 reset Driver. 4. Cadence QSPI controller Driver. 5. MMC SPI Driver for MMC/SD support. +6. PLDA PCIE controller driver. +7. On-board VL805 PCIE-USB controller driver. Booting from MMC using U-Boot SPL --------------------------------- diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a1e089962a..8c54bc9c47 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -218,6 +218,7 @@ config DEBUG_UART choice prompt "Select which UART will provide the debug UART" depends on DEBUG_UART + default DEBUG_SBI_CONSOLE if RISCV_SMODE default DEBUG_UART_NS16550 config DEBUG_UART_ALTERA_JTAGUART @@ -289,11 +290,13 @@ config DEBUG_EFI_CONSOLE config DEBUG_SBI_CONSOLE bool "SBI" - depends on SBI_V01 + depends on RISCV_SMODE help Select this to enable a debug console which calls back to SBI to output to the console. This can be useful for early debugging of U-Boot when running on top of SBI (Supervisor Binary Interface). + This implementation of the debug UART is not available while in + M-mode (e.g. during SPL). config DEBUG_UART_S5P bool "Samsung S5P" diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c index b9f35ed36e..a51a96c1ef 100644 --- a/drivers/serial/serial_sbi.c +++ b/drivers/serial/serial_sbi.c @@ -3,6 +3,8 @@ #include <debug_uart.h> #include <asm/sbi.h> +#ifdef CONFIG_SBI_V01 + static inline void _debug_uart_init(void) { } @@ -13,4 +15,22 @@ static inline void _debug_uart_putc(int c) sbi_console_putchar(c); } +#else + +static int sbi_dbcn_available; + +static inline void _debug_uart_init(void) +{ + if (CONFIG_IS_ENABLED(RISCV_SMODE)) + sbi_dbcn_available = sbi_probe_extension(SBI_EXT_DBCN); +} + +static inline void _debug_uart_putc(int ch) +{ + if (CONFIG_IS_ENABLED(RISCV_SMODE) && sbi_dbcn_available) + sbi_dbcn_write_byte(ch); +} + +#endif + DEBUG_UART_FUNCS diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 3627ed79b8..28a6a6870b 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -13,6 +13,7 @@ #include <common.h> #include <dm.h> #include <errno.h> +#include <fdt_support.h> #include <timer.h> #include <asm/csr.h> @@ -53,9 +54,26 @@ u64 notrace timer_early_get_count(void) static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + u32 rate; - /* clock frequency was passed from the cpu driver as driver data */ - uc_priv->clock_rate = dev->driver_data; + /* When this function was called from the CPU driver, clock + * frequency is passed as driver data. + */ + rate = dev->driver_data; + + /* When called from an FDT match, the rate needs to be looked up. */ + if (!rate && gd->fdt_blob) { + rate = fdt_getprop_u32_default(gd->fdt_blob, + "/cpus", "timebase-frequency", 0); + } + + uc_priv->clock_rate = rate; + + /* With rate==0, timer uclass post_probe might later fail with -EINVAL. + * Give a hint at the cause for debugging. + */ + if (!rate) + log_err("riscv_timer_probe with invalid clock rate 0!\n"); return 0; } @@ -64,9 +82,15 @@ static const struct timer_ops riscv_timer_ops = { .get_count = riscv_timer_get_count, }; +static const struct udevice_id riscv_timer_ids[] = { + { .compatible = "riscv,timer", }, + { } +}; + U_BOOT_DRIVER(riscv_timer) = { .name = "riscv_timer", .id = UCLASS_TIMER, + .of_match = of_match_ptr(riscv_timer_ids), .probe = riscv_timer_probe, .ops = &riscv_timer_ops, .flags = DM_FLAG_PRE_RELOC, diff --git a/include/spl.h b/include/spl.h index 92bcaa90a4..93e906431e 100644 --- a/include/spl.h +++ b/include/spl.h @@ -862,7 +862,7 @@ void __noreturn spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); /** * spl_invoke_opensbi - boot using a RISC-V OpenSBI image */ -void spl_invoke_opensbi(struct spl_image_info *spl_image); +void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image); /** * board_return_to_bootrom - allow for boards to continue with the boot ROM |