diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2021-10-12 11:43:00 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2021-10-15 15:57:31 +0300 |
| commit | f2cdd44adb9f06f455185b4882cfd91e8d75d58a (patch) | |
| tree | 089bd253b6b62f1c75c355d0f2bfdc0e56e1e48c | |
| parent | 24c627b57a090b141a3088208e3f70b6f28dc3d8 (diff) | |
| download | u-boot-f2cdd44adb9f06f455185b4882cfd91e8d75d58a.tar.xz | |
clk: rockchip: rk3568: update clks
fix up ppll init freq.
support tclk_emmc.
add freq (26M) for mmc device.
fix up the sfc clk rate unit error.
Change in V2:
remove change id.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 11 |
2 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 6c59033f03..399f19ad21 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -14,7 +14,7 @@ #define APLL_HZ (816 * MHz) #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (1000 * MHz) -#define PPLL_HZ (100 * MHz) +#define PPLL_HZ (200 * MHz) /* RK3568 pll id */ enum rk3568_pll_id { diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 553c6c0daf..d5e45e7602 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1441,6 +1441,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, switch (rate) { case OSC_HZ: + case 26 * MHz: src_clk = CLK_SDMMC_SEL_24M; break; case 400 * MHz: @@ -1507,7 +1508,7 @@ static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv) case SCLK_SFC_SEL_125M: return 125 * MHz; case SCLK_SFC_SEL_150M: - return 150 * KHz; + return 150 * MHz; default: return -ENOENT; } @@ -1534,7 +1535,7 @@ static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) case 125 * MHz: src_clk = SCLK_SFC_SEL_125M; break; - case 150 * KHz: + case 150 * MHz: src_clk = SCLK_SFC_SEL_150M; break; default: @@ -2406,6 +2407,9 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case BCLK_EMMC: rate = rk3568_emmc_get_bclk(priv); break; + case TCLK_EMMC: + rate = OSC_HZ; + break; #ifndef CONFIG_SPL_BUILD case ACLK_VOP: rate = rk3568_aclk_vop_get_clk(priv); @@ -2582,6 +2586,9 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case BCLK_EMMC: ret = rk3568_emmc_set_bclk(priv, rate); break; + case TCLK_EMMC: + ret = OSC_HZ; + break; #ifndef CONFIG_SPL_BUILD case ACLK_VOP: ret = rk3568_aclk_vop_set_clk(priv, rate); |