diff options
| author | Peter Hoyes <Peter.Hoyes@arm.com> | 2021-07-12 17:04:21 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-07-24 01:53:46 +0300 |
| commit | c48fec6e7c6ba173f42c9e8b70c001862e048220 (patch) | |
| tree | 0b9cf7df29c0f751cc53c61c9ed7d6026d1ea518 | |
| parent | ad7e967738a9c639e07cf50b83ffccdf9a8537b0 (diff) | |
| download | u-boot-c48fec6e7c6ba173f42c9e8b70c001862e048220.tar.xz | |
armv8: Initialize CNTFRQ if at highest exception level
CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.
This patch moves the initialization outside of the switch_el
block and uses a new macro branch_if_not_highest_el which
dynamically detects whether it is at the highest supported
exception level.
Linux's docs state that CNTFRQ_EL0 should be initialized by the
bootloader. If not set, the the U-Boot prompt countdown hangs.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/macro.h | 18 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 6 |
3 files changed, 32 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 9e9c6140cd..b3eef705a5 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -127,10 +127,6 @@ pie_fixup_done: orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ -#ifdef COUNTER_FREQUENCY - ldr x0, =COUNTER_FREQUENCY - msr cntfrq_el0, x0 /* Initialize CNTFRQ */ -#endif b 0f 2: mrs x1, hcr_el2 tbnz x1, #34, 1f /* HCR_EL2.E2H */ @@ -142,7 +138,14 @@ pie_fixup_done: mov x0, #3 << 20 msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: - isb + +#ifdef COUNTER_FREQUENCY + branch_if_not_highest_el x0, 4f + ldr x0, =COUNTER_FREQUENCY + msr cntfrq_el0, x0 /* Initialize CNTFRQ */ +#endif + +4: isb /* * Enable SMPEN bit for coherency. diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index bb33b4bc89..485310d660 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -78,6 +78,24 @@ lr .req x30 .endm /* + * Branch if we are not in the highest exception level + */ +.macro branch_if_not_highest_el, xreg, label + switch_el \xreg, 3f, 2f, 1f + +2: mrs \xreg, ID_AA64PFR0_EL1 + and \xreg, \xreg, #(ID_AA64PFR0_EL1_EL3) + cbnz \xreg, \label + b 3f + +1: mrs \xreg, ID_AA64PFR0_EL1 + and \xreg, \xreg, #(ID_AA64PFR0_EL1_EL3 | ID_AA64PFR0_EL1_EL2) + cbnz \xreg, \label + +3: +.endm + +/* * Branch if current processor is a Cortex-A57 core. */ .macro branch_if_a57_core, xreg, a57_label diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 11fceec4d2..8b3a54e64c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -80,6 +80,12 @@ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ /* + * ID_AA64PFR0_EL1 bits definitions + */ +#define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */ +#define ID_AA64PFR0_EL1_EL2 (0xF << 8) /* EL2 implemented */ + +/* * CPACR_EL1 bits definitions */ #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */ |