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authorMasahisa Kojima <masahisa.kojima@linaro.org>2023-05-24 10:32:46 +0300
committerJagan Teki <jagan@edgeble.ai>2023-07-13 11:29:57 +0300
commit1d70101aa2a489529847231c741dff4f235cfeaa (patch)
treea90c1d7a9677bb946a1c94e8d8dbe8f78798dcd5
parent55c0144bd30dbbb9a3b1cb6987040022756368f2 (diff)
downloadu-boot-1d70101aa2a489529847231c741dff4f235cfeaa.tar.xz
spi: synquacer: remove SPI_TX_BYTE handling
Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
-rw-r--r--drivers/spi/spi-synquacer.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index 0f5d0a30c3..553f9687e3 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
struct udevice *bus = dev->parent;
struct synquacer_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
- u32 val, div, bus_width = 1;
+ u32 val, div, bus_width;
int rwflag;
rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
@@ -203,16 +203,14 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
priv->mode = slave_plat->mode;
priv->speed = slave_plat->max_hz;
- if (priv->mode & SPI_TX_BYTE)
- bus_width = 1;
- else if (priv->mode & SPI_TX_DUAL)
+ if (priv->mode & SPI_TX_DUAL)
bus_width = 2;
else if (priv->mode & SPI_TX_QUAD)
bus_width = 4;
else if (priv->mode & SPI_TX_OCTAL)
bus_width = 8;
else
- log_warning("SPI mode not configured, setting to byte mode\n");
+ bus_width = 1; /* default is single bit mode */
div = DIV_ROUND_UP(125000000, priv->speed);