diff options
| author | Tom Rini <trini@konsulko.com> | 2022-12-03 00:42:40 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-22 18:31:48 +0300 |
| commit | 2b210540b13ab528fbccc0122605ef07a57881af (patch) | |
| tree | 73c7154cb02c9ddb24bf589a1475ac9c7bac95e3 | |
| parent | 0a69d6afcab9b2fa364cd78aa67340185c5f75a0 (diff) | |
| download | u-boot-2b210540b13ab528fbccc0122605ef07a57881af.tar.xz | |
Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig
This converts the following to Kconfig:
CONFIG_PEN_ADDR_BIG_ENDIAN
Signed-off-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/Kconfig | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 3 | ||||
| -rw-r--r-- | include/configs/ls1021aiot.h | 1 | ||||
| -rw-r--r-- | include/configs/ls1021aqds.h | 1 | ||||
| -rw-r--r-- | include/configs/ls1021atwr.h | 1 |
5 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8381e09e10..6e191e41d5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1599,6 +1599,7 @@ config TARGET_LS1021AQDS select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select SYS_FSL_DDR select FSL_DDR_INTERACTIVE @@ -1617,6 +1618,7 @@ config TARGET_LS1021ATWR select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER @@ -1681,6 +1683,7 @@ config TARGET_LS1021AIOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 7e138e0cc5..a83eb7e8fd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -51,6 +51,9 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config PEN_ADDR_BIG_ENDIAN + bool + config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 179c5128e3..0e3ff3c5b7 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -68,7 +68,6 @@ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index fead9edecc..76e75335c5 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -242,7 +242,6 @@ * MMC */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b07978a999..281b26fa2b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -152,7 +152,6 @@ /* GPIO */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 |