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| author | Simon Glass <sjg@chromium.org> | 2020-07-19 22:55:56 +0300 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2020-07-29 04:30:39 +0300 |
| commit | 4183eee3f681f9fe0788f2bbaf3da1515aeac78c (patch) | |
| tree | d1e79a00ef4ac24b797fd854ad6dcca2e9ec78bf | |
| parent | eba768c545870619a811fe3a4e4635a0fcebc2a6 (diff) | |
| download | u-boot-4183eee3f681f9fe0788f2bbaf3da1515aeac78c.tar.xz | |
rockchip: bob: Support SPI-flash booting
Update the config for chromebook_bob to support booting from SPI flash.
The existing SPL size is too small since ATF is needed, so double it.
Signed-off-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | configs/chromebook_bob_defconfig | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 3f560ebb63..3026b56f91 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 @@ -40,6 +40,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -53,6 +54,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y |