diff options
| author | Damon Ding <damon.ding@rock-chips.com> | 2023-08-04 12:33:57 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-08-12 05:35:35 +0300 |
| commit | acb9812034850ae0d737a767b392b9cd097f3606 (patch) | |
| tree | c0e436d37dd63af59046ca101ec673ed810dedbe | |
| parent | 6e710897aa319cda8aaf18a09290e3fb9b6d015f (diff) | |
| download | u-boot-acb9812034850ae0d737a767b392b9cd097f3606.tar.xz | |
clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk
Fix use of wrong clk selection for CLK_PWM1 on RK3568.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 0df82f5971..e8e4d20e53 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1142,7 +1142,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id) switch (clk_id) { case CLK_PWM1: - sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; break; case CLK_PWM2: sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; |