diff options
author | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-07-10 15:55:21 +0300 |
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committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-10-09 12:53:10 +0300 |
commit | d3e829b6183a857b9f5b7626ae6af2eaff95c555 (patch) | |
tree | f058cedc0f866f0d6472f55eaf4d3d46464a2ab3 | |
parent | 36162a8eb8962e9447e9ad03b5103a3a66228476 (diff) | |
download | u-boot-d3e829b6183a857b9f5b7626ae6af2eaff95c555.tar.xz |
clk: agilex: Add clock enable support
Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.
Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
-rw-r--r-- | drivers/clk/altera/clk-agilex.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index d7402999ef..36a224d762 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -542,6 +542,11 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } } +static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + static int socfpga_clk_probe(struct udevice *dev) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -565,6 +570,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) } static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, .get_rate = socfpga_clk_get_rate, }; |