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| author | William Qiu <william.qiu@starfivetech.com> | 2023-07-28 13:16:10 +0300 |
|---|---|---|
| committer | William Qiu <william.qiu@starfivetech.com> | 2023-07-28 13:16:10 +0300 |
| commit | f29800c842e7d38c1d056edb2b34fbbcedc4ddf6 (patch) | |
| tree | c19bbf31e0859e1636cbc7e42eb2c28cb238d36d | |
| parent | 8ac919d8c4ea5550752f9ad3b64d6396395ee50c (diff) | |
| download | u-boot-f29800c842e7d38c1d056edb2b34fbbcedc4ddf6.tar.xz | |
riscv: dts: starfive: limit cclk_in frequency
The frequency of cclk_in is limited to 50M, so that it does not do internal
part frequency and goes by-pass mode. And delete syscon node.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
| -rw-r--r-- | arch/riscv/dts/starfive_visionfive2.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts index 34bdd57eab..e1429b45dd 100644 --- a/arch/riscv/dts/starfive_visionfive2.dts +++ b/arch/riscv/dts/starfive_visionfive2.dts @@ -294,6 +294,8 @@ }; &sdio0 { + assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>; + assigned-clock-rates = <50000000>; fifo-depth = <32>; bus-width = <8>; pinctrl-names = "default"; @@ -302,6 +304,8 @@ }; &sdio1 { + assigned-clocks = <&clkgen JH7110_SDIO1_CLK_SDCARD>; + assigned-clock-rates = <50000000>; fifo-depth = <32>; bus-width = <4>; pinctrl-names = "default"; |