diff options
| author | Julien Panis <jpanis@baylibre.com> | 2023-05-29 16:42:28 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-06-20 23:08:13 +0300 |
| commit | fb93bd8d264c3198f321dc23a83559fcfcc275d4 (patch) | |
| tree | 5b78e6f5ae34e161dad180cd384a956f03c25355 | |
| parent | 8dc2c666808a07c2ad484ef6c4f89aa551eaf265 (diff) | |
| download | u-boot-fb93bd8d264c3198f321dc23a83559fcfcc275d4.tar.xz | |
drivers: spi: omap3_spi: Initialize mode for all channels
At first SPI transfers, multiple chip selects can be
enabled simultaneously. This is due to chip select
polarity, which is not properly initialized for all
channels. This patch fixes the issue.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
| -rw-r--r-- | drivers/spi/omap3_spi.c | 20 | ||||
| -rw-r--r-- | include/omap3_spi.h | 4 |
2 files changed, 17 insertions, 7 deletions
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 1cbb5d46fd..ff7b55f870 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -347,20 +347,28 @@ static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) omap3_spi_write_chconf(priv, confr); } -static void spi_reset(struct mcspi *regs) +static void spi_reset(struct omap3_spi_priv *priv) { unsigned int tmp; - writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); + writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &priv->regs->sysconfig); do { - tmp = readl(®s->sysstatus); + tmp = readl(&priv->regs->sysstatus); } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE)); writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE | OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP | - OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); + OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &priv->regs->sysconfig); - writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); + writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &priv->regs->wakeupenable); + + /* + * Set the same default mode for each channel, especially CS polarity + * which must be common for all SPI slaves before any transfer. + */ + for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++) + _omap3_spi_set_mode(priv); + priv->cs = 0; } static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) @@ -430,7 +438,7 @@ static int omap3_spi_probe(struct udevice *dev) priv->pin_dir = plat->pin_dir; priv->wordlen = SPI_DEFAULT_WORDLEN; - spi_reset(priv->regs); + spi_reset(priv); return 0; } diff --git a/include/omap3_spi.h b/include/omap3_spi.h index cae3770583..5381431d43 100644 --- a/include/omap3_spi.h +++ b/include/omap3_spi.h @@ -46,6 +46,8 @@ #define OMAP4_MCSPI_REG_OFFSET 0x100 +#define OMAP4_MCSPI_CHAN_NB 4 + /* OMAP3 McSPI registers */ struct mcspi_channel { unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ @@ -64,7 +66,7 @@ struct mcspi { unsigned int wakeupenable; /* 0x20 */ unsigned int syst; /* 0x24 */ unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; + struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ /* channel1: 0x40 - 0x50, bus 0 & 1 */ /* channel2: 0x54 - 0x64, bus 0 & 1 */ |