diff options
| author | Tom Rini <trini@konsulko.com> | 2022-02-11 01:38:04 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-02-11 01:38:04 +0300 |
| commit | fe203a05fb663fa9bc42a9ef9ae51a6ed01a4a90 (patch) | |
| tree | 635b4c3019d51684bdb98a52e20aaeb893c5c40a | |
| parent | c4408291bfff9622f2d3817a13c997debd0e8200 (diff) | |
| parent | ad41ed120893522e23cc24550bb2d1dfb745a075 (diff) | |
| download | u-boot-fe203a05fb663fa9bc42a9ef9ae51a6ed01a4a90.tar.xz | |
Merge branch '2022-02-10-platform-updates'
- Assorted Apple M1 platform updates
- Drop CONFIG_SYS_RESET_ADDR, update k3-am64-sk memory values in dts
172 files changed, 1592 insertions, 249 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9a62b55786..8053394389 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -931,7 +931,10 @@ config ARCH_APPLE select DM select DM_GPIO select DM_KEYBOARD + select DM_MAILBOX + select DM_RESET select DM_SERIAL + select DM_SPI select DM_USB select DM_VIDEO select IOMMU @@ -941,6 +944,7 @@ config ARCH_APPLE select POSITION_INDEPENDENT select POWER_DOMAIN select REGMAP + select SPI select SYSCON select SYSRESET select SYSRESET_WATCHDOG diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi index 64a159f6d0..dde5ab150d 100644 --- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi +++ b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi @@ -2,8 +2,8 @@ /* * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00 - * Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 + * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz * Density (per channel): 16Gb @@ -268,8 +268,8 @@ #define DDRSS_CTL_251_DATA 0x00000000 #define DDRSS_CTL_252_DATA 0x00000000 #define DDRSS_CTL_253_DATA 0x00000000 -#define DDRSS_CTL_254_DATA 0x66006666 -#define DDRSS_CTL_255_DATA 0x00002766 +#define DDRSS_CTL_254_DATA 0x46004646 +#define DDRSS_CTL_255_DATA 0x00002746 #define DDRSS_CTL_256_DATA 0x00000027 #define DDRSS_CTL_257_DATA 0x00000027 #define DDRSS_CTL_258_DATA 0x00000027 @@ -660,13 +660,13 @@ #define DDRSS_PI_220_DATA 0x000000A7 #define DDRSS_PI_221_DATA 0x00001900 #define DDRSS_PI_222_DATA 0x32000056 -#define DDRSS_PI_223_DATA 0x06000301 +#define DDRSS_PI_223_DATA 0x06000101 #define DDRSS_PI_224_DATA 0x001D0204 #define DDRSS_PI_225_DATA 0x32120059 -#define DDRSS_PI_226_DATA 0x05000301 +#define DDRSS_PI_226_DATA 0x05000101 #define DDRSS_PI_227_DATA 0x001D0409 #define DDRSS_PI_228_DATA 0x32120059 -#define DDRSS_PI_229_DATA 0x05000301 +#define DDRSS_PI_229_DATA 0x05000101 #define DDRSS_PI_230_DATA 0x00000409 #define DDRSS_PI_231_DATA 0x05030900 #define DDRSS_PI_232_DATA 0x00040900 @@ -748,7 +748,7 @@ #define DDRSS_PI_308_DATA 0x00000031 #define DDRSS_PI_309_DATA 0x00000000 #define DDRSS_PI_310_DATA 0x00000000 -#define DDRSS_PI_311_DATA 0x66000000 +#define DDRSS_PI_311_DATA 0x46000000 #define DDRSS_PI_312_DATA 0x00150F27 #define DDRSS_PI_313_DATA 0x00000000 #define DDRSS_PI_314_DATA 0x00000024 @@ -756,7 +756,7 @@ #define DDRSS_PI_316_DATA 0x00000031 #define DDRSS_PI_317_DATA 0x00000000 #define DDRSS_PI_318_DATA 0x00000000 -#define DDRSS_PI_319_DATA 0x66000000 +#define DDRSS_PI_319_DATA 0x46000000 #define DDRSS_PI_320_DATA 0x00150F27 #define DDRSS_PI_321_DATA 0x00000000 #define DDRSS_PI_322_DATA 0x00000004 @@ -772,7 +772,7 @@ #define DDRSS_PI_332_DATA 0x00000031 #define DDRSS_PI_333_DATA 0x00000000 #define DDRSS_PI_334_DATA 0x00000000 -#define DDRSS_PI_335_DATA 0x66000000 +#define DDRSS_PI_335_DATA 0x46000000 #define DDRSS_PI_336_DATA 0x00150F27 #define DDRSS_PI_337_DATA 0x00000000 #define DDRSS_PI_338_DATA 0x00000024 @@ -780,7 +780,7 @@ #define DDRSS_PI_340_DATA 0x00000031 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x00000000 -#define DDRSS_PI_343_DATA 0x66000000 +#define DDRSS_PI_343_DATA 0x46000000 #define DDRSS_PI_344_DATA 0x00150F27 #define DDRSS_PHY_0_DATA 0x04F00000 #define DDRSS_PHY_1_DATA 0x00000000 @@ -873,7 +873,7 @@ #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 -#define DDRSS_PHY_91_DATA 0x0100C0C0 +#define DDRSS_PHY_91_DATA 0x0000C0C0 #define DDRSS_PHY_92_DATA 0x03040000 #define DDRSS_PHY_93_DATA 0x00000403 #define DDRSS_PHY_94_DATA 0x42100010 @@ -1129,7 +1129,7 @@ #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 -#define DDRSS_PHY_347_DATA 0x0100C0C0 +#define DDRSS_PHY_347_DATA 0x0000C0C0 #define DDRSS_PHY_348_DATA 0x03040000 #define DDRSS_PHY_349_DATA 0x00000403 #define DDRSS_PHY_350_DATA 0x42100010 @@ -2157,7 +2157,7 @@ #define DDRSS_PHY_1372_DATA 0x00000002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 -#define DDRSS_PHY_1375_DATA 0x030207AB +#define DDRSS_PHY_1375_DATA 0x03020000 #define DDRSS_PHY_1376_DATA 0x00000080 #define DDRSS_PHY_1377_DATA 0x03900390 #define DDRSS_PHY_1378_DATA 0x03900390 diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h new file mode 100644 index 0000000000..51f77f298c --- /dev/null +++ b/arch/arm/include/asm/arch-apple/rtkit.h @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> + */ + +#define APPLE_RTKIT_PWR_STATE_SLEEP 0x01 +#define APPLE_RTKIT_PWR_STATE_QUIESCED 0x10 +#define APPLE_RTKIT_PWR_STATE_ON 0x20 + +int apple_rtkit_init(struct mbox_chan *); +int apple_rtkit_shutdown(struct mbox_chan *, int); diff --git a/arch/arm/include/asm/arch-m1/uart.h b/arch/arm/include/asm/arch-apple/uart.h index d2a17a221e..d2a17a221e 100644 --- a/arch/arm/include/asm/arch-m1/uart.h +++ b/arch/arm/include/asm/arch-apple/uart.h diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig index 80e8eb2307..75ee21e0f4 100644 --- a/arch/arm/mach-apple/Kconfig +++ b/arch/arm/mach-apple/Kconfig @@ -7,7 +7,7 @@ config SYS_CONFIG_NAME default "apple" config SYS_SOC - default "m1" + default "apple" config SYS_MALLOC_LEN default 0x4000000 diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Makefile index e74a8c9df1..52f30a777b 100644 --- a/arch/arm/mach-apple/Makefile +++ b/arch/arm/mach-apple/Makefile @@ -2,3 +2,4 @@ obj-y += board.o obj-y += lowlevel_init.o +obj-y += rtkit.o diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c new file mode 100644 index 0000000000..dff475cab7 --- /dev/null +++ b/arch/arm/mach-apple/rtkit.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> + * (C) Copyright 2021 Copyright The Asahi Linux Contributors + */ + +#include <common.h> +#include <mailbox.h> +#include <malloc.h> + +#include <asm/arch/rtkit.h> +#include <linux/apple-mailbox.h> +#include <linux/bitfield.h> + +#define APPLE_RTKIT_EP_MGMT 0 +#define APPLE_RTKIT_EP_CRASHLOG 1 +#define APPLE_RTKIT_EP_SYSLOG 2 +#define APPLE_RTKIT_EP_DEBUG 3 +#define APPLE_RTKIT_EP_IOREPORT 4 + +/* Messages for management endpoint. */ +#define APPLE_RTKIT_MGMT_TYPE GENMASK(59, 52) + +#define APPLE_RTKIT_MGMT_PWR_STATE GENMASK(15, 0) + +#define APPLE_RTKIT_MGMT_HELLO 1 +#define APPLE_RTKIT_MGMT_HELLO_REPLY 2 +#define APPLE_RTKIT_MGMT_HELLO_MINVER GENMASK(15, 0) +#define APPLE_RTKIT_MGMT_HELLO_MAXVER GENMASK(31, 16) + +#define APPLE_RTKIT_MGMT_STARTEP 5 +#define APPLE_RTKIT_MGMT_STARTEP_EP GENMASK(39, 32) +#define APPLE_RTKIT_MGMT_STARTEP_FLAG BIT(1) + +#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6 +#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7 + +#define APPLE_RTKIT_MGMT_EPMAP 8 +#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51) +#define APPLE_RTKIT_MGMT_EPMAP_BASE GENMASK(34, 32) +#define APPLE_RTKIT_MGMT_EPMAP_BITMAP GENMASK(31, 0) + +#define APPLE_RTKIT_MGMT_EPMAP_REPLY 8 +#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0) + +#define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11 +#define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12 + +/* Messages for internal endpoints. */ +#define APPLE_RTKIT_BUFFER_REQUEST 1 +#define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK(51, 44) +#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK(41, 0) + +int apple_rtkit_init(struct mbox_chan *chan) +{ + struct apple_mbox_msg msg; + int endpoints[256]; + int nendpoints = 0; + int endpoint; + int min_ver, max_ver, want_ver; + int msgtype, pwrstate; + u64 reply; + u32 bitmap, base; + int i, ret; + + /* Wakup the IOP. */ + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) | + FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, APPLE_RTKIT_PWR_STATE_ON); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + + /* Wait for protocol version negotiation message. */ + ret = mbox_recv(chan, &msg, 10000); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + if (msgtype != APPLE_RTKIT_MGMT_HELLO) { + printf("%s: unexpected message type %d\n", __func__, msgtype); + return -EINVAL; + } + + min_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MINVER, msg.msg0); + max_ver = FIELD_GET(APPLE_RTKIT_MGMT_HELLO_MAXVER, msg.msg0); + want_ver = min(APPLE_RTKIT_MAX_SUPPORTED_VERSION, max_ver); + + if (min_ver > APPLE_RTKIT_MAX_SUPPORTED_VERSION) { + printf("%s: firmware min version %d is too new\n", + __func__, min_ver); + return -ENOTSUPP; + } + + if (max_ver < APPLE_RTKIT_MIN_SUPPORTED_VERSION) { + printf("%s: firmware max version %d is too old\n", + __func__, max_ver); + return -ENOTSUPP; + } + + /* Ack version. */ + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_HELLO_REPLY) | + FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MINVER, want_ver) | + FIELD_PREP(APPLE_RTKIT_MGMT_HELLO_MAXVER, want_ver); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + +wait_epmap: + /* Wait for endpoint map message. */ + ret = mbox_recv(chan, &msg, 10000); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + if (msgtype != APPLE_RTKIT_MGMT_EPMAP) { + printf("%s: unexpected message type %d\n", __func__, msgtype); + return -EINVAL; + } + + bitmap = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BITMAP, msg.msg0); + base = FIELD_GET(APPLE_RTKIT_MGMT_EPMAP_BASE, msg.msg0); + for (i = 0; i < 32; i++) { + if (bitmap & (1U << i)) + endpoints[nendpoints++] = base * 32 + i; + } + + /* Ack endpoint map. */ + reply = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_EPMAP_REPLY) | + FIELD_PREP(APPLE_RTKIT_MGMT_EPMAP_BASE, base); + if (msg.msg0 & APPLE_RTKIT_MGMT_EPMAP_LAST) + reply |= APPLE_RTKIT_MGMT_EPMAP_LAST; + else + reply |= APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE; + msg.msg0 = reply; + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + + if (reply & APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE) + goto wait_epmap; + + for (i = 0; i < nendpoints; i++) { + /* Don't start the syslog endpoint since we can't + easily handle its messages in U-Boot. */ + if (endpoints[i] == APPLE_RTKIT_EP_SYSLOG) + continue; + + /* Request endpoint. */ + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_STARTEP) | + FIELD_PREP(APPLE_RTKIT_MGMT_STARTEP_EP, endpoints[i]) | + APPLE_RTKIT_MGMT_STARTEP_FLAG; + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + } + + pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP; + while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) { + ret = mbox_recv(chan, &msg, 100000); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + + if (endpoint == APPLE_RTKIT_EP_CRASHLOG || + endpoint == APPLE_RTKIT_EP_SYSLOG || + endpoint == APPLE_RTKIT_EP_IOREPORT) { + u64 addr = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg.msg0); + u64 size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg.msg0); + + if (msgtype == APPLE_RTKIT_BUFFER_REQUEST && addr != 0) + continue; + + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) | + FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, size) | + FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, addr); + msg.msg1 = endpoint; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + continue; + } + + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) { + printf("%s: unexpected message type %d\n", __func__, msgtype); + return -EINVAL; + } + + pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0); + } + + return 0; +} + +int apple_rtkit_shutdown(struct mbox_chan *chan, int pwrstate) +{ + struct apple_mbox_msg msg; + int ret; + + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) | + FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(chan, &msg); + if (ret < 0) + return ret; + + ret = mbox_recv(chan, &msg, 100000); + if (ret < 0) + return ret; + + return 0; +} diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 893aecef21..6d16ed084e 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -215,19 +215,12 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* + * * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address. - * Better pick an address known to be invalid on your system and assign - * it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... */ addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); -#endif + ((void (*)(void)) addr)(); return 1; } diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index cb235e4e7d..8583e4ad8c 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_APPLE=y CONFIG_DEFAULT_DEVICE_TREE="t8103-j274" CONFIG_DEBUG_UART_BASE=0x235200000 -CONFIG_DEBUG_UART_CLOCK=240000 +CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_SYS_LOAD_ADDR=0x880000000 CONFIG_USE_PREBOOT=y @@ -11,8 +11,10 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_NET is not set # CONFIG_MMC is not set CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_NVME_APPLE=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_KEYBOARD=y +CONFIG_APPLE_SPI_KEYB=y CONFIG_VIDEO_SIMPLE=y # CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 6e344c9ce3..6dcd70fe12 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -56,7 +56,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index d576b5c38d..fe1c019f1d 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index 34f352f2d8..45cefd85e0 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -62,7 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index a694005412..0c3fd6ddb3 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -60,7 +60,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index 5d17cd18da..f85e2eebe7 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -48,7 +48,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 4d22db224e..b2bdf96922 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -62,7 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index e3763666d7..085919b974 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -60,7 +60,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index f76138f910..c416245025 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -48,7 +48,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MDIO_MUX_MESON_G12A=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MESON=y CONFIG_MESON_G12A_USB_PHY=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 520ab1baa0..b61276cf1d 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_RV8803=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index ad3b7bff42..0b3964e9d8 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 3317a0592b..93514082f2 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 6eaf0f5788..f25c22e926 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index facbb26f0d..343e38df08 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 6e2118fda1..16bb10e625 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 5370c32129..4ced1bfa5b 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index bac3f91610..91bfab0862 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -72,7 +72,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 476ebd0415..14eeade305 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 057c0475ae..3531fa7b93 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -73,7 +73,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 771d69e17a..227668912b 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -52,7 +52,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 83ba8ee542..23370901a1 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -57,7 +57,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 19550ea1b1..bdd8c9a6ff 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -54,7 +54,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 3df6dd21a6..94408c32b9 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -56,7 +56,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 5943fb6a48..911b4dba3a 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -54,7 +54,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index e9e3ee9441..f72f2b1bb5 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -71,7 +71,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index d587c35a43..925d68db8e 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -76,7 +76,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index ebf724a409..c71c8649d9 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index d5a306e5c6..58629beb0c 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -99,7 +99,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 3fcd53320f..d252ed49e9 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -75,7 +75,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index dda02ae48a..fb9f457b74 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 188f125429..1d6d88ff37 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -78,7 +78,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 9dad311417..f629080be2 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 25afa72f21..38b17048c4 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -95,7 +95,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 3dd2912171..eb97c18fdd 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -85,7 +85,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 42210602f9..45b05adbb4 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -59,7 +59,7 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_SJA1105=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 627038cb6e..7bc1963b2f 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -75,7 +75,7 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_SJA1105=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 0c64cf08f3..2f66d833a3 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 39ba7bef26..c1adc6e23f 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -65,7 +65,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index de3183c8dd..150179d633 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -66,7 +66,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 38f0731d22..016771a8f6 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -64,7 +64,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index e43e2ba8c5..695505a975 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 429adf3e48..19e7751e78 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index bbb6f1aff6..af65bcad84 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -73,7 +73,7 @@ CONFIG_DM_DSA=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_MDIO_MUX_I2CREG=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 2b90d8a0df..bc473ae143 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -79,7 +79,7 @@ CONFIG_DM_DSA=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_MDIO_MUX_I2CREG=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 84696fc13d..417c848124 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -78,7 +78,7 @@ CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_FSL_ENETC=y CONFIG_MDIO_MUX_I2CREG=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 7fc8bec434..8b5bb130f6 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -68,7 +68,7 @@ CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 56535904ea..2018d15a83 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -74,7 +74,7 @@ CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 342dea5fcd..ef1a591ec0 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index dd8188a72b..8dd6ce41d6 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 6de0666ba5..3e54803107 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 60f9e16ca9..97fe2ce8bd 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 9724cf96df..dd0a726502 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -76,7 +76,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index aa5ae5e137..be40f49f6e 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -100,7 +100,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index ebbcd74a47..5820444404 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -93,7 +93,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 15cb28ba95..e196c4428f 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 9bffcf7fe0..6a89794885 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -92,7 +92,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index e2762cd0cf..e7c277d6c6 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -65,7 +65,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 8f3155bd69..94daa1f10b 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -68,7 +68,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index b3c1505f5e..a86138f179 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 1780675891..19a54d1ea2 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -88,7 +88,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 4977b4e2d2..ef82842b64 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index d8d65b813b..6ff5614cb5 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -66,7 +66,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index b68c125271..551807e879 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -72,7 +72,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index a2ebe525ed..30daa5c6d0 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -60,7 +60,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 8e19249f61..c15302c753 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index f8b4faafc7..bc326114cd 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -82,7 +82,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 37b45ee063..52855d12e5 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index e0e736fa8b..ab780c1622 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 99177d7638..8111ce6432 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 83c6c93ed9..b5b501c9a9 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -102,7 +102,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 291ca2ff74..01451930e6 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -95,7 +95,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 92f3b1797d..740838baa1 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -83,7 +83,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 7ac9406737..11de0d40af 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -93,7 +93,7 @@ CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index fe06a2e328..a319bf39fc 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -85,7 +85,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index eb94ca3b98..92769655d5 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -68,7 +68,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 41e735da90..506b32c248 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -72,7 +72,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 3b4a939c6b..87ab8ac421 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -90,7 +90,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index eb43d79c12..033ccc24e6 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 7e847c88f5..f841053fd8 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -64,7 +64,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 867acb2481..2a3f6cb328 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -70,7 +70,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index f51bc3d123..094f11363f 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 6f6206ba7f..9b51ee98f3 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -76,7 +76,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 68de77e238..4187ff7564 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index ac0601a96d..c594d783ed 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -91,7 +91,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 3a4f696dd8..1e83ab444b 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index d4abdb3ff9..56b6da647c 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -102,7 +102,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index c4ae4b5a2d..f84a63bd29 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -77,7 +77,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index f3c0191213..976d65bfbf 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -80,7 +80,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 566e1eb193..a0c5d97ac5 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -90,7 +90,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 53244a881d..6f983fd753 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -78,7 +78,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index e2f975bb92..4ba4507d34 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -84,7 +84,7 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 45fe718596..ace5820f33 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -69,7 +69,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index b695f8a6f0..d21a136c20 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -72,7 +72,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 57622e6af6..82cd933103 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -79,7 +79,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index fc0afefa7c..0ac2b835e9 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index f24f0038a0..42e0cb22c0 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -74,7 +74,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 0e84f89ddf..81cd8b4402 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -68,7 +68,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x580980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index d350a3111c..a7491ccb3a 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -71,7 +71,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x580980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 41b6684a7f..bc297e57ef 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -80,7 +80,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 2a8a562f60..a2a14194b6 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -64,7 +64,7 @@ CONFIG_PHY_CORTINA=y CONFIG_CORTINA_FW_ADDR=0x980000 CONFIG_E1000=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index e247f498a3..c8d7e670e3 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -90,7 +90,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index e75fa0e541..193990c2a3 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -67,7 +67,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 788930086b..ee8510914d 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -74,7 +74,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 032b133cc4..de37147aae 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index ffc3a7b2ef..f4902a12fe 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -87,7 +87,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index d5b8168fe1..17e04c4d22 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -82,7 +82,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index b8addd592b..f12ad8fac3 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -89,7 +89,7 @@ CONFIG_E1000=y CONFIG_MII=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index f53480cf7a..52bd909b04 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -74,7 +74,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 8798f3e4a5..3760fef4a8 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -83,7 +83,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index a46d44dc08..db5fda3060 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -83,7 +83,7 @@ CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_MII=y CONFIG_FSL_LS_MDIO=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index 039fd8b3dc..f1215fa359 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -62,7 +62,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index e6168a76a6..622d687e5d 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -51,7 +51,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 42d7038c5a..1789838691 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -67,7 +67,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index ffe6518433..4b8206a38f 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -73,7 +73,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVNETA=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_AARDVARK=y CONFIG_PHY=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 2aa06f80a0..f45ce91f6f 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -56,7 +56,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index 053b2f4c96..af01e6176a 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -60,7 +60,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVPP2=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_MVEBU=y CONFIG_PHY=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index f31668c5c2..3b3da3870b 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -37,7 +37,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 1298bfe309..1ce892d963 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -99,7 +99,7 @@ CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y CONFIG_NET_OCTEONTX2=y CONFIG_OCTEONTX_SMI=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SRIOV=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index ba8cc97ab8..ddb9007bf1 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -99,7 +99,7 @@ CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y CONFIG_NET_OCTEONTX=y CONFIG_OCTEONTX_SMI=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SRIOV=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 26759341c5..b8ebc2812e 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -96,7 +96,7 @@ CONFIG_E1000_SPI=y CONFIG_CMD_E1000=y CONFIG_NET_OCTEONTX=y CONFIG_OCTEONTX_SMI=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SRIOV=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index e4265d6321..46f4cd0110 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_RTL8169=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 81aedb28e3..d7378f5eb3 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -56,7 +56,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 6d1a6ba66f..591b31165f 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -60,7 +60,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_CPU=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index b0cf701996..928fa68e2d 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_CPU=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 8f86f19e89..606a7fdee0 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -48,7 +48,7 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_SCSI=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 653c76ba61..febf8f2806 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -50,7 +50,7 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_ETH=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_SCSI=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index f60ddf0097..d4dc8ecc51 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -81,7 +81,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_RCAR_GEN3=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index ca2fb9e13f..b79200fd3b 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -49,7 +49,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 9a3b8f781d..4f15627d59 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index a27799f343..0381a1ca3f 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index bd8b1201ef..c066d9160a 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -42,7 +42,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index e46f07e74d..d95da51891 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -42,7 +42,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 637c5c2466..d5e98a4f73 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -48,7 +48,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index d82c180420..7c157a23d0 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -167,7 +167,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 68e958216e..7ebeb89264 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -209,7 +209,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_MULTIPLEXER=y CONFIG_MUX_MMIO=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SANDBOX=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index d809712308..217b0647bb 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -136,7 +136,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SANDBOX=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index b288ac2685..ec912cf0ec 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -163,7 +163,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index cd1ad386ac..1687ccf453 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -165,7 +165,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 299580894c..86f8c7856e 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -44,7 +44,7 @@ CONFIG_SPL_CLK=y CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_SPI_FLASH_ISSI=y CONFIG_E1000=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_DW_SIFIVE=y CONFIG_DM_RESET=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index da57dc288f..fe12c74374 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -69,7 +69,7 @@ CONFIG_PHY_GIGE=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_SNI_NETSEC=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 415387b189..84a0b4c2b2 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -79,7 +79,7 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_AARDVARK=y CONFIG_PHY=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index d6f70caeaf..938683616b 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -78,7 +78,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y -CONFIG_NVME=y +CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y diff --git a/doc/develop/driver-model/nvme.rst b/doc/develop/driver-model/nvme.rst index 736c0a063d..fd0c0f00d2 100644 --- a/doc/develop/driver-model/nvme.rst +++ b/doc/develop/driver-model/nvme.rst @@ -40,6 +40,7 @@ It only support basic block read/write functions in the NVMe driver. Config options -------------- CONFIG_NVME Enable NVMe device support +CONFIG_NVME_PCI Enable PCIe NVMe device support CONFIG_CMD_NVME Enable basic NVMe commands Usage in U-Boot diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 0b753f37bf..2718b3674a 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -47,6 +47,14 @@ config KEYBOARD and is only used by novena. For new boards, use driver model instead. +config APPLE_SPI_KEYB + bool "Enable Apple SPI keyboard support" + depends on DM_KEYBOARD && DM_SPI + help + This adds a driver for the keyboards found on various + laptops based on Apple SoCs. These keyboards use an + Apple-specific HID-over-SPI protocol. + config CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support" depends on INPUT diff --git a/drivers/input/Makefile b/drivers/input/Makefile index e440c921e4..b1133f772f 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o obj-$(CONFIG_I8042_KEYB) += i8042.o obj-$(CONFIG_TEGRA_KEYBOARD) += input.o tegra-kbc.o obj-$(CONFIG_TWL4030_INPUT) += twl4030.o diff --git a/drivers/input/apple_spi_kbd.c b/drivers/input/apple_spi_kbd.c new file mode 100644 index 0000000000..7cf12f453a --- /dev/null +++ b/drivers/input/apple_spi_kbd.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org> + */ + +#include <common.h> +#include <dm.h> +#include <keyboard.h> +#include <spi.h> +#include <stdio_dev.h> +#include <asm-generic/gpio.h> +#include <linux/delay.h> +#include <linux/input.h> + +/* + * The Apple SPI keyboard controller implements a protocol that + * closely resembles HID Keyboard Boot protocol. The key codes are + * mapped according to the HID Keyboard/Keypad Usage Table. + */ + +/* Modifier key bits */ +#define HID_MOD_LEFTCTRL BIT(0) +#define HID_MOD_LEFTSHIFT BIT(1) +#define HID_MOD_LEFTALT BIT(2) +#define HID_MOD_LEFTGUI BIT(3) +#define HID_MOD_RIGHTCTRL BIT(4) +#define HID_MOD_RIGHTSHIFT BIT(5) +#define HID_MOD_RIGHTALT BIT(6) +#define HID_MOD_RIGHTGUI BIT(7) + +static const u8 hid_kbd_keymap[] = { + KEY_RESERVED, 0xff, 0xff, 0xff, + KEY_A, KEY_B, KEY_C, KEY_D, + KEY_E, KEY_F, KEY_G, KEY_H, + KEY_I, KEY_J, KEY_K, KEY_L, + KEY_M, KEY_N, KEY_O, KEY_P, + KEY_Q, KEY_R, KEY_S, KEY_T, + KEY_U, KEY_V, KEY_W, KEY_X, + KEY_Y, KEY_Z, KEY_1, KEY_2, + KEY_3, KEY_4, KEY_5, KEY_6, + KEY_7, KEY_8, KEY_9, KEY_0, + KEY_ENTER, KEY_ESC, KEY_BACKSPACE, KEY_TAB, + KEY_SPACE, KEY_MINUS, KEY_EQUAL, KEY_LEFTBRACE, + KEY_RIGHTBRACE, KEY_BACKSLASH, 0xff, KEY_SEMICOLON, + KEY_APOSTROPHE, KEY_GRAVE, KEY_COMMA, KEY_DOT, + KEY_SLASH, KEY_CAPSLOCK, KEY_F1, KEY_F2, + KEY_F3, KEY_F4, KEY_F5, KEY_F6, + KEY_F7, KEY_F8, KEY_F9, KEY_F10, + KEY_F11, KEY_F12, KEY_SYSRQ, KEY_SCROLLLOCK, + KEY_PAUSE, KEY_INSERT, KEY_HOME, KEY_PAGEUP, + KEY_DELETE, KEY_END, KEY_PAGEDOWN, KEY_RIGHT, + KEY_LEFT, KEY_DOWN, KEY_UP, KEY_NUMLOCK, + KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS, KEY_KPPLUS, + KEY_KPENTER, KEY_KP1, KEY_KP2, KEY_KP3, + KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7, + KEY_KP8, KEY_KP9, KEY_KP0, KEY_KPDOT, + KEY_BACKSLASH, KEY_COMPOSE, KEY_POWER, KEY_KPEQUAL, +}; + +/* Report ID used for keyboard input reports. */ +#define KBD_REPORTID 0x01 + +struct apple_spi_kbd_report { + u8 reportid; + u8 modifiers; + u8 reserved; + u8 keycode[6]; + u8 fn; +}; + +struct apple_spi_kbd_priv { + struct gpio_desc enable; + struct apple_spi_kbd_report old; /* previous keyboard input report */ + struct apple_spi_kbd_report new; /* current keyboard input report */ +}; + +/* Keyboard device. */ +#define KBD_DEVICE 0x01 + +/* The controller sends us fixed-size packets of 256 bytes. */ +struct apple_spi_kbd_packet { + u8 flags; +#define PACKET_READ 0x20 + u8 device; + u16 offset; + u16 remaining; + u16 len; + u8 data[246]; + u16 crc; +}; + +/* Packets contain a single variable-sized message. */ +struct apple_spi_kbd_msg { + u8 type; +#define MSG_REPORT 0x10 + u8 device; + u8 unknown; + u8 msgid; + u16 rsplen; + u16 cmdlen; + u8 data[0]; +}; + +static void apple_spi_kbd_service_modifiers(struct input_config *input) +{ + struct apple_spi_kbd_priv *priv = dev_get_priv(input->dev); + u8 new = priv->new.modifiers; + u8 old = priv->old.modifiers; + + if ((new ^ old) & HID_MOD_LEFTCTRL) + input_add_keycode(input, KEY_LEFTCTRL, + old & HID_MOD_LEFTCTRL); + if ((new ^ old) & HID_MOD_RIGHTCTRL) + input_add_keycode(input, KEY_RIGHTCTRL, + old & HID_MOD_RIGHTCTRL); + if ((new ^ old) & HID_MOD_LEFTSHIFT) + input_add_keycode(input, KEY_LEFTSHIFT, + old & HID_MOD_LEFTSHIFT); + if ((new ^ old) & HID_MOD_RIGHTSHIFT) + input_add_keycode(input, KEY_RIGHTSHIFT, + old & HID_MOD_RIGHTSHIFT); + if ((new ^ old) & HID_MOD_LEFTALT) + input_add_keycode(input, KEY_LEFTALT, + old & HID_MOD_LEFTALT); + if ((new ^ old) & HID_MOD_RIGHTALT) + input_add_keycode(input, KEY_RIGHTALT, + old & HID_MOD_RIGHTALT); + if ((new ^ old) & HID_MOD_LEFTGUI) + input_add_keycode(input, KEY_LEFTMETA, + old & HID_MOD_LEFTGUI); + if ((new ^ old) & HID_MOD_RIGHTGUI) + input_add_keycode(input, KEY_RIGHTMETA, + old & HID_MOD_RIGHTGUI); +} + +static void apple_spi_kbd_service_key(struct input_config *input, int i, + int released) +{ + struct apple_spi_kbd_priv *priv = dev_get_priv(input->dev); + u8 *new; + u8 *old; + + if (released) { + new = priv->new.keycode; + old = priv->old.keycode; + } else { + new = priv->old.keycode; + old = priv->new.keycode; + } + + if (memscan(new, old[i], sizeof(priv->new.keycode)) == + new + sizeof(priv->new.keycode) && + old[i] < ARRAY_SIZE(hid_kbd_keymap)) + input_add_keycode(input, hid_kbd_keymap[old[i]], released); +} + +static int apple_spi_kbd_check(struct input_config *input) +{ + struct udevice *dev = input->dev; + struct apple_spi_kbd_priv *priv = dev_get_priv(dev); + struct apple_spi_kbd_packet packet; + struct apple_spi_kbd_msg *msg; + struct apple_spi_kbd_report *report; + int i, ret; + + memset(&packet, 0, sizeof(packet)); + + ret = dm_spi_claim_bus(dev); + if (ret < 0) + return ret; + + /* + * The keyboard controller needs delays after asserting CS# + * and before deasserting CS#. + */ + ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN); + if (ret < 0) + goto fail; + udelay(100); + ret = dm_spi_xfer(dev, sizeof(packet) * 8, NULL, &packet, 0); + if (ret < 0) + goto fail; + udelay(100); + ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + if (ret < 0) + goto fail; + + dm_spi_release_bus(dev); + + /* + * The keyboard controller needs a delay between subsequent + * SPI transfers. + */ + udelay(250); + + msg = (struct apple_spi_kbd_msg *)packet.data; + report = (struct apple_spi_kbd_report *)msg->data; + if (packet.flags == PACKET_READ && packet.device == KBD_DEVICE && + msg->type == MSG_REPORT && msg->device == KBD_DEVICE && + msg->cmdlen == sizeof(struct apple_spi_kbd_report) && + report->reportid == KBD_REPORTID) { + memcpy(&priv->new, report, + sizeof(struct apple_spi_kbd_report)); + apple_spi_kbd_service_modifiers(input); + for (i = 0; i < sizeof(priv->new.keycode); i++) { + apple_spi_kbd_service_key(input, i, 1); + apple_spi_kbd_service_key(input, i, 0); + } + memcpy(&priv->old, &priv->new, + sizeof(struct apple_spi_kbd_report)); + return 1; + } + + return 0; + +fail: + /* + * Make sure CS# is deasserted. If this fails there is nothing + * we can do, so ignore any errors. + */ + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); + return ret; +} + +static int apple_spi_kbd_probe(struct udevice *dev) +{ + struct apple_spi_kbd_priv *priv = dev_get_priv(dev); + struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev); + struct stdio_dev *sdev = &uc_priv->sdev; + struct input_config *input = &uc_priv->input; + int ret; + + ret = gpio_request_by_name(dev, "spien-gpios", 0, &priv->enable, + GPIOD_IS_OUT); + if (ret < 0) + return ret; + + /* Reset the keyboard controller. */ + dm_gpio_set_value(&priv->enable, 1); + udelay(5000); + dm_gpio_set_value(&priv->enable, 0); + udelay(5000); + + /* Enable the keyboard controller. */ + dm_gpio_set_value(&priv->enable, 1); + + input->dev = dev; + input->read_keys = apple_spi_kbd_check; + input_add_tables(input, false); + strcpy(sdev->name, "spikbd"); + + return input_stdio_register(sdev); +} + +static const struct keyboard_ops apple_spi_kbd_ops = { +}; + +static const struct udevice_id apple_spi_kbd_of_match[] = { + { .compatible = "apple,spi-hid-transport" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_spi_kbd) = { + .name = "apple_spi_kbd", + .id = UCLASS_KEYBOARD, + .of_match = apple_spi_kbd_of_match, + .probe = apple_spi_kbd_probe, + .priv_auto = sizeof(struct apple_spi_kbd_priv), + .ops = &apple_spi_kbd_ops, +}; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index dd4b0ac0c3..73db2af0b8 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -10,6 +10,17 @@ config DM_MAILBOX the basis of a variety of inter-process/inter-CPU communication protocols. +config APPLE_MBOX + bool "Enable Apple IOP controller support" + depends on DM_MAILBOX && ARCH_APPLE + default y + help + Enable support for the mailboxes that provide a comminucation + channel with Apple IOP controllers integrated on Apple SoCs. + These IOP controllers are used to implement various functions + such as the System Management Controller (SMC) and NVMe and this + driver is required to get that functionality up and running. + config SANDBOX_MBOX bool "Enable the sandbox mailbox test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index d2ace8cd21..59e8d0de93 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o +obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o diff --git a/drivers/mailbox/apple-mbox.c b/drivers/mailbox/apple-mbox.c new file mode 100644 index 0000000000..30c8e2f03f --- /dev/null +++ b/drivers/mailbox/apple-mbox.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org> + */ + +#include <common.h> +#include <dm.h> +#include <mailbox-uclass.h> +#include <asm/io.h> +#include <linux/apple-mailbox.h> +#include <linux/delay.h> + +#define REG_A2I_STAT 0x110 +#define REG_A2I_STAT_EMPTY BIT(17) +#define REG_A2I_STAT_FULL BIT(16) +#define REG_I2A_STAT 0x114 +#define REG_I2A_STAT_EMPTY BIT(17) +#define REG_I2A_STAT_FULL BIT(16) +#define REG_A2I_MSG0 0x800 +#define REG_A2I_MSG1 0x808 +#define REG_I2A_MSG0 0x830 +#define REG_I2A_MSG1 0x838 + +struct apple_mbox_priv { + void *base; +}; + +static int apple_mbox_of_xlate(struct mbox_chan *chan, + struct ofnode_phandle_args *args) +{ + if (args->args_count != 0) + return -EINVAL; + + return 0; +} + +static int apple_mbox_send(struct mbox_chan *chan, const void *data) +{ + struct apple_mbox_priv *priv = dev_get_priv(chan->dev); + const struct apple_mbox_msg *msg = data; + + writeq(msg->msg0, priv->base + REG_A2I_MSG0); + writeq(msg->msg1, priv->base + REG_A2I_MSG1); + while (readl(priv->base + REG_A2I_STAT) & REG_A2I_STAT_FULL) + udelay(1); + + return 0; +} + +static int apple_mbox_recv(struct mbox_chan *chan, void *data) +{ + struct apple_mbox_priv *priv = dev_get_priv(chan->dev); + struct apple_mbox_msg *msg = data; + + if (readl(priv->base + REG_I2A_STAT) & REG_I2A_STAT_EMPTY) + return -ENODATA; + + msg->msg0 = readq(priv->base + REG_I2A_MSG0); + msg->msg1 = readq(priv->base + REG_I2A_MSG1); + return 0; +} + +struct mbox_ops apple_mbox_ops = { + .of_xlate = apple_mbox_of_xlate, + .send = apple_mbox_send, + .recv = apple_mbox_recv, +}; + +static int apple_mbox_probe(struct udevice *dev) +{ + struct apple_mbox_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id apple_mbox_of_match[] = { + { .compatible = "apple,asc-mailbox-v4" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_mbox) = { + .name = "apple-mbox", + .id = UCLASS_MAILBOX, + .of_match = apple_mbox_of_match, + .probe = apple_mbox_probe, + .priv_auto = sizeof(struct apple_mbox_priv), + .ops = &apple_mbox_ops, +}; diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 1f6d1f5648..0cb465160b 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -4,8 +4,27 @@ config NVME bool "NVM Express device support" - depends on BLK && PCI + depends on BLK select HAVE_BLOCK_DEVICE help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). + +config NVME_APPLE + bool "Apple NVMe controller support" + select NVME + help + This option enables support for the NVMe storage + controller integrated on Apple SoCs. This controller + isn't PCI-based based and deviates from the NVMe + standard implementation in its implementation of + the command submission queue and the integration + of an NVMMU that needs to be managed. + +config NVME_PCI + bool "NVM Express PCI device support" + depends on PCI + select NVME + help + This option enables support for NVM Express PCI + devices. diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile index 64f102b208..fa7b619446 100644 --- a/drivers/nvme/Makefile +++ b/drivers/nvme/Makefile @@ -3,3 +3,5 @@ # Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> obj-y += nvme-uclass.o nvme.o nvme_show.o +obj-$(CONFIG_NVME_APPLE) += nvme_apple.o +obj-$(CONFIG_NVME_PCI) += nvme_pci.o diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 3c529a2fce..1d56517e99 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -12,7 +12,6 @@ #include <log.h> #include <malloc.h> #include <memalign.h> -#include <pci.h> #include <time.h> #include <dm/device-internal.h> #include <linux/compat.h> @@ -28,33 +27,6 @@ #define IO_TIMEOUT 30 #define MAX_PRP_POOL 512 -enum nvme_queue_id { - NVME_ADMIN_Q, - NVME_IO_Q, - NVME_Q_NUM, -}; - -/* - * An NVM Express queue. Each device has at least two (one for admin - * commands and one for I/O commands). - */ -struct nvme_queue { - struct nvme_dev *dev; - struct nvme_command *sq_cmds; - struct nvme_completion *cqes; - wait_queue_head_t sq_full; - u32 __iomem *q_db; - u16 q_depth; - s16 cq_vector; - u16 sq_head; - u16 sq_tail; - u16 cq_head; - u16 qid; - u8 cq_phase; - u8 cqe_seen; - unsigned long cmdid_data[]; -}; - static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) { u32 bit = enabled ? NVME_CSTS_RDY : 0; @@ -168,12 +140,19 @@ static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index) */ static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) { + struct nvme_ops *ops; u16 tail = nvmeq->sq_tail; memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); flush_dcache_range((ulong)&nvmeq->sq_cmds[tail], (ulong)&nvmeq->sq_cmds[tail] + sizeof(*cmd)); + ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops; + if (ops && ops->submit_cmd) { + ops->submit_cmd(nvmeq, cmd); + return; + } + if (++tail == nvmeq->q_depth) tail = 0; writel(tail, nvmeq->q_db); @@ -184,6 +163,7 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, u32 *result, unsigned timeout) { + struct nvme_ops *ops; u16 head = nvmeq->cq_head; u16 phase = nvmeq->cq_phase; u16 status; @@ -204,6 +184,10 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, return -ETIMEDOUT; } + ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops; + if (ops && ops->complete_cmd) + ops->complete_cmd(nvmeq, cmd); + status >>= 1; if (status) { printf("ERROR: status = %x, phase = %d, head = %d\n", @@ -244,6 +228,7 @@ static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) { + struct nvme_ops *ops; struct nvme_queue *nvmeq = malloc(sizeof(*nvmeq)); if (!nvmeq) return NULL; @@ -269,6 +254,10 @@ static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, dev->queue_count++; dev->queues[qid] = nvmeq; + ops = (struct nvme_ops *)dev->udev->driver->ops; + if (ops && ops->setup_queue) + ops->setup_queue(nvmeq); + return nvmeq; free_queue: @@ -698,7 +687,6 @@ static int nvme_blk_probe(struct udevice *udev) struct blk_desc *desc = dev_get_uclass_plat(udev); struct nvme_ns *ns = dev_get_priv(udev); u8 flbas; - struct pci_child_plat *pplat; struct nvme_id_ns *id; id = memalign(ndev->page_size, sizeof(struct nvme_id_ns)); @@ -723,8 +711,7 @@ static int nvme_blk_probe(struct udevice *udev) desc->log2blksz = ns->lba_shift; desc->blksz = 1 << ns->lba_shift; desc->bdev = udev; - pplat = dev_get_parent_plat(udev->parent); - sprintf(desc->vendor, "0x%.4x", pplat->vendor); + memcpy(desc->vendor, ndev->vendor, sizeof(ndev->vendor)); memcpy(desc->product, ndev->serial, sizeof(ndev->serial)); memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev)); @@ -818,27 +805,14 @@ U_BOOT_DRIVER(nvme_blk) = { .priv_auto = sizeof(struct nvme_ns), }; -static int nvme_bind(struct udevice *udev) -{ - static int ndev_num; - char name[20]; - - sprintf(name, "nvme#%d", ndev_num++); - - return device_set_name(udev, name); -} - -static int nvme_probe(struct udevice *udev) +int nvme_init(struct udevice *udev) { - int ret; struct nvme_dev *ndev = dev_get_priv(udev); struct nvme_id_ns *id; + int ret; - ndev->instance = trailing_strtol(udev->name); - + ndev->udev = udev; INIT_LIST_HEAD(&ndev->namespaces); - ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); if (readl(&ndev->bar->csts) == -1) { ret = -ENODEV; printf("Error: %s: Out of memory!\n", udev->name); @@ -923,17 +897,9 @@ free_nvme: return ret; } -U_BOOT_DRIVER(nvme) = { - .name = "nvme", - .id = UCLASS_NVME, - .bind = nvme_bind, - .probe = nvme_probe, - .priv_auto = sizeof(struct nvme_dev), -}; - -struct pci_device_id nvme_supported[] = { - { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) }, - {} -}; +int nvme_shutdown(struct udevice *udev) +{ + struct nvme_dev *ndev = dev_get_priv(udev); -U_BOOT_PCI_DEVICE(nvme, nvme_supported); + return nvme_disable_ctrl(ndev); +} diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h index c6aae4da5d..bc1d612dde 100644 --- a/drivers/nvme/nvme.h +++ b/drivers/nvme/nvme.h @@ -596,6 +596,7 @@ enum { /* Represents an NVM Express device. Each nvme_dev is a PCI function. */ struct nvme_dev { + struct udevice *udev; struct list_head node; struct nvme_queue **queues; u32 __iomem *dbs; @@ -608,6 +609,7 @@ struct nvme_dev { u32 ctrl_config; struct nvme_bar __iomem *bar; struct list_head namespaces; + char vendor[8]; char serial[20]; char model[40]; char firmware_rev[8]; @@ -621,6 +623,33 @@ struct nvme_dev { u32 nn; }; +/* Admin queue and a single I/O queue. */ +enum nvme_queue_id { + NVME_ADMIN_Q, + NVME_IO_Q, + NVME_Q_NUM, +}; + +/* + * An NVM Express queue. Each device has at least two (one for admin + * commands and one for I/O commands). + */ +struct nvme_queue { + struct nvme_dev *dev; + struct nvme_command *sq_cmds; + struct nvme_completion *cqes; + u32 __iomem *q_db; + u16 q_depth; + s16 cq_vector; + u16 sq_head; + u16 sq_tail; + u16 cq_head; + u16 qid; + u8 cq_phase; + u8 cqe_seen; + unsigned long cmdid_data[]; +}; + /* * An NVM Express namespace is equivalent to a SCSI LUN. * Each namespace is operated as an independent "device". @@ -635,4 +664,45 @@ struct nvme_ns { u8 flbas; }; +struct nvme_ops { + /** + * setup_queue - Controller-specific NVM Express queue setup. + * + * @nvmeq: NVM Express queue + * Return: 0 if OK, -ve on error + */ + int (*setup_queue)(struct nvme_queue *nvmeq); + /** + * submit_cmd - Controller-specific NVM Express command submission. + * + * If this function pointer is set to NULL, normal command + * submission is performed according to the NVM Express spec. + * + * @nvmeq: NVM Express queue + * @cmd: NVM Express command + */ + void (*submit_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd); + /** + * complete_cmd - Controller-specific NVM Express command completion + * + * @nvmeq: NVM Express queue + * @cmd: NVM Express command + */ + void (*complete_cmd)(struct nvme_queue *nvmeq, struct nvme_command *cmd); +}; + +/** + * nvme_init() - Initialize NVM Express device + * @udev: The NVM Express device + * Return: 0 if OK, -ve on error + */ +int nvme_init(struct udevice *udev); + +/** + * nvme_shutdown() - Shutdown NVM Express device + * @udev: The NVM Express device + * Return: 0 if OK, -ve on error + */ +int nvme_shutdown(struct udevice *udev); + #endif /* __DRIVER_NVME_H__ */ diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c new file mode 100644 index 0000000000..d9d491c2be --- /dev/null +++ b/drivers/nvme/nvme_apple.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> + */ + +#include <common.h> +#include <dm.h> +#include <mailbox.h> +#include <mapmem.h> +#include "nvme.h" +#include <reset.h> + +#include <asm/io.h> +#include <asm/arch/rtkit.h> +#include <linux/iopoll.h> + +/* ASC registers */ +#define REG_CPU_CTRL 0x0044 +#define REG_CPU_CTRL_RUN BIT(4) + +/* Apple NVMe registers */ +#define ANS_MAX_PEND_CMDS_CTRL 0x01210 +#define ANS_MAX_QUEUE_DEPTH 64 +#define ANS_BOOT_STATUS 0x01300 +#define ANS_BOOT_STATUS_OK 0xde71ce55 +#define ANS_MODESEL 0x01304 +#define ANS_UNKNOWN_CTRL 0x24008 +#define ANS_PRP_NULL_CHECK (1 << 11) +#define ANS_LINEAR_SQ_CTRL 0x24908 +#define ANS_LINEAR_SQ_CTRL_EN (1 << 0) +#define ANS_ASQ_DB 0x2490c +#define ANS_IOSQ_DB 0x24910 +#define ANS_NVMMU_NUM 0x28100 +#define ANS_NVMMU_BASE_ASQ 0x28108 +#define ANS_NVMMU_BASE_IOSQ 0x28110 +#define ANS_NVMMU_TCB_INVAL 0x28118 +#define ANS_NVMMU_TCB_STAT 0x28120 + +#define ANS_NVMMU_TCB_SIZE 0x4000 +#define ANS_NVMMU_TCB_PITCH 0x80 + +/* + * The Apple NVMe controller includes an IOMMU known as NVMMU. The + * NVMMU is programmed through an array of TCBs. These TCBs are paired + * with the corresponding slot in the submission queues and need to be + * configured with the command details before a command is allowed to + * execute. This is necessary even for commands that don't do DMA. + */ +struct ans_nvmmu_tcb { + u8 opcode; + u8 flags; + u8 slot; + u8 pad0; + u32 prpl_len; + u8 pad1[16]; + u64 prp1; + u64 prp2; +}; + +#define ANS_NVMMU_TCB_WRITE BIT(0) +#define ANS_NVMMU_TCB_READ BIT(1) + +struct apple_nvme_priv { + struct nvme_dev ndev; + void *base; /* NVMe registers */ + void *asc; /* ASC registers */ + struct reset_ctl_bulk resets; /* ASC reset */ + struct mbox_chan chan; + struct ans_nvmmu_tcb *tcbs[NVME_Q_NUM]; /* Submission queue TCBs */ + u32 __iomem *q_db[NVME_Q_NUM]; /* Submission queue doorbell */ +}; + +static int apple_nvme_setup_queue(struct nvme_queue *nvmeq) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct nvme_dev *dev = nvmeq->dev; + + switch (nvmeq->qid) { + case NVME_ADMIN_Q: + case NVME_IO_Q: + break; + default: + return -EINVAL; + } + + priv->tcbs[nvmeq->qid] = (void *)memalign(4096, ANS_NVMMU_TCB_SIZE); + memset((void *)priv->tcbs[nvmeq->qid], 0, ANS_NVMMU_TCB_SIZE); + + switch (nvmeq->qid) { + case NVME_ADMIN_Q: + priv->q_db[nvmeq->qid] = + ((void __iomem *)dev->bar) + ANS_ASQ_DB; + nvme_writeq((ulong)priv->tcbs[nvmeq->qid], + ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_ASQ); + break; + case NVME_IO_Q: + priv->q_db[nvmeq->qid] = + ((void __iomem *)dev->bar) + ANS_IOSQ_DB; + nvme_writeq((ulong)priv->tcbs[nvmeq->qid], + ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_IOSQ); + break; + } + + return 0; +} + +static void apple_nvme_submit_cmd(struct nvme_queue *nvmeq, + struct nvme_command *cmd) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct ans_nvmmu_tcb *tcb; + u16 tail = nvmeq->sq_tail; + + tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH; + memset(tcb, 0, sizeof(*tcb)); + tcb->opcode = cmd->common.opcode; + tcb->flags = ANS_NVMMU_TCB_WRITE | ANS_NVMMU_TCB_READ; + tcb->slot = tail; + tcb->prpl_len = cmd->rw.length; + tcb->prp1 = cmd->common.prp1; + tcb->prp2 = cmd->common.prp2; + + writel(tail, priv->q_db[nvmeq->qid]); +} + +static void apple_nvme_complete_cmd(struct nvme_queue *nvmeq, + struct nvme_command *cmd) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct ans_nvmmu_tcb *tcb; + u16 tail = nvmeq->sq_tail; + + tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH; + memset(tcb, 0, sizeof(*tcb)); + writel(tail, ((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_INVAL); + readl(((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_STAT); + + if (++tail == nvmeq->q_depth) + tail = 0; + nvmeq->sq_tail = tail; +} + +static int apple_nvme_probe(struct udevice *dev) +{ + struct apple_nvme_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + u32 ctrl, stat; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->asc = map_sysmem(addr, 0); + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) + return ret; + + ret = mbox_get_by_index(dev, 0, &priv->chan); + if (ret < 0) + return ret; + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + ret = apple_rtkit_init(&priv->chan); + if (ret < 0) + return ret; + + ret = readl_poll_sleep_timeout(priv->base + ANS_BOOT_STATUS, stat, + (stat == ANS_BOOT_STATUS_OK), 100, + 500000); + if (ret < 0) { + printf("%s: NVMe firmware didn't boot\n", __func__); + return -ETIMEDOUT; + } + + writel(ANS_LINEAR_SQ_CTRL_EN, priv->base + ANS_LINEAR_SQ_CTRL); + writel(((ANS_MAX_QUEUE_DEPTH << 16) | ANS_MAX_QUEUE_DEPTH), + priv->base + ANS_MAX_PEND_CMDS_CTRL); + + writel(readl(priv->base + ANS_UNKNOWN_CTRL) & ~ANS_PRP_NULL_CHECK, + priv->base + ANS_UNKNOWN_CTRL); + + strcpy(priv->ndev.vendor, "Apple"); + + writel((ANS_NVMMU_TCB_SIZE / ANS_NVMMU_TCB_PITCH) - 1, + priv->base + ANS_NVMMU_NUM); + writel(0, priv->base + ANS_MODESEL); + + priv->ndev.bar = priv->base; + return nvme_init(dev); +} + +static int apple_nvme_remove(struct udevice *dev) +{ + struct apple_nvme_priv *priv = dev_get_priv(dev); + u32 ctrl; + + nvme_shutdown(dev); + + apple_rtkit_shutdown(&priv->chan, APPLE_RTKIT_PWR_STATE_SLEEP); + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + reset_assert_bulk(&priv->resets); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static const struct nvme_ops apple_nvme_ops = { + .setup_queue = apple_nvme_setup_queue, + .submit_cmd = apple_nvme_submit_cmd, + .complete_cmd = apple_nvme_complete_cmd, +}; + +static const struct udevice_id apple_nvme_ids[] = { + { .compatible = "apple,nvme-ans2" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_nvme) = { + .name = "apple_nvme", + .id = UCLASS_NVME, + .of_match = apple_nvme_ids, + .priv_auto = sizeof(struct apple_nvme_priv), + .probe = apple_nvme_probe, + .remove = apple_nvme_remove, + .ops = &apple_nvme_ops, + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c new file mode 100644 index 0000000000..5f60fb884f --- /dev/null +++ b/drivers/nvme/nvme_pci.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 NXP Semiconductors + * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <pci.h> +#include "nvme.h" + +static int nvme_bind(struct udevice *udev) +{ + static int ndev_num; + char name[20]; + + sprintf(name, "nvme#%d", ndev_num++); + + return device_set_name(udev, name); +} + +static int nvme_probe(struct udevice *udev) +{ + struct nvme_dev *ndev = dev_get_priv(udev); + struct pci_child_plat *pplat; + + pplat = dev_get_parent_plat(udev); + sprintf(ndev->vendor, "0x%.4x", pplat->vendor); + + ndev->instance = trailing_strtol(udev->name); + ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + return nvme_init(udev); +} + +U_BOOT_DRIVER(nvme) = { + .name = "nvme", + .id = UCLASS_NVME, + .bind = nvme_bind, + .probe = nvme_probe, + .priv_auto = sizeof(struct nvme_dev), +}; + +struct pci_device_id nvme_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) }, + {} +}; + +U_BOOT_PCI_DEVICE(nvme, nvme_supported); diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index d25f136b9d..4d06e76ff5 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -6,14 +6,22 @@ #include <common.h> #include <asm/io.h> #include <dm.h> +#include <dm/device-internal.h> #include <linux/err.h> #include <linux/bitfield.h> #include <power-domain-uclass.h> +#include <reset-uclass.h> #include <regmap.h> #include <syscon.h> -#define APPLE_PMGR_PS_TARGET GENMASK(3, 0) +#define APPLE_PMGR_RESET BIT(31) +#define APPLE_PMGR_DEV_DISABLE BIT(10) +#define APPLE_PMGR_WAS_CLKGATED BIT(9) +#define APPLE_PMGR_WAS_PWRGATED BIT(8) #define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4) +#define APPLE_PMGR_PS_TARGET GENMASK(3, 0) + +#define APPLE_PMGR_FLAGS (APPLE_PMGR_WAS_CLKGATED | APPLE_PMGR_WAS_PWRGATED) #define APPLE_PMGR_PS_ACTIVE 0xf #define APPLE_PMGR_PS_PWRGATE 0x0 @@ -25,6 +33,65 @@ struct apple_pmgr_priv { u32 offset; /* offset within regmap for this domain */ }; +static int apple_reset_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + if (args->args_count != 0) + return -EINVAL; + + return 0; +} + +static int apple_reset_request(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int apple_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int apple_reset_assert(struct reset_ctl *reset_ctl) +{ + struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent); + + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, + APPLE_PMGR_DEV_DISABLE); + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, + APPLE_PMGR_RESET); + + return 0; +} + +static int apple_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct apple_pmgr_priv *priv = dev_get_priv(reset_ctl->dev->parent); + + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, 0); + regmap_update_bits(priv->regmap, priv->offset, + APPLE_PMGR_FLAGS | APPLE_PMGR_DEV_DISABLE, 0); + + return 0; +} + +struct reset_ops apple_reset_ops = { + .of_xlate = apple_reset_of_xlate, + .request = apple_reset_request, + .rfree = apple_reset_free, + .rst_assert = apple_reset_assert, + .rst_deassert = apple_reset_deassert, +}; + +static struct driver apple_reset_driver = { + .name = "apple_reset", + .id = UCLASS_RESET, + .ops = &apple_reset_ops, +}; + static int apple_pmgr_request(struct power_domain *power_domain) { return 0; @@ -78,6 +145,7 @@ static const struct udevice_id apple_pmgr_ids[] = { static int apple_pmgr_probe(struct udevice *dev) { struct apple_pmgr_priv *priv = dev_get_priv(dev); + struct udevice *child; int ret; ret = dev_power_domain_on(dev); @@ -92,6 +160,9 @@ static int apple_pmgr_probe(struct udevice *dev) if (ret < 0) return ret; + device_bind(dev, &apple_reset_driver, "apple_reset", NULL, + dev_ofnode(dev), &child); + return 0; } diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d07e9a28af..0a6a85f9c4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -50,6 +50,13 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config APPLE_SPI + bool "Apple SPI driver" + default y if ARCH_APPLE + help + Enable the Apple SPI driver. This driver can be used to + access the SPI flash and keyboard on machines based on Apple SoCs. + config ATCSPI200_SPI bool "Andestech ATCSPI200 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d2f24bccef..bea746f3e3 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o +obj-$(CONFIG_APPLE_SPI) += apple_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c new file mode 100644 index 0000000000..f35f5af1f6 --- /dev/null +++ b/drivers/spi/apple_spi.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org> + * Copyright The Asahi Linux Contributors + */ + +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <spi.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/delay.h> + +#define APPLE_SPI_CTRL 0x000 +#define APPLE_SPI_CTRL_RUN BIT(0) +#define APPLE_SPI_CTRL_TX_RESET BIT(2) +#define APPLE_SPI_CTRL_RX_RESET BIT(3) + +#define APPLE_SPI_CFG 0x004 +#define APPLE_SPI_CFG_CPHA BIT(1) +#define APPLE_SPI_CFG_CPOL BIT(2) +#define APPLE_SPI_CFG_MODE GENMASK(6, 5) +#define APPLE_SPI_CFG_MODE_POLLED 0 +#define APPLE_SPI_CFG_MODE_IRQ 1 +#define APPLE_SPI_CFG_MODE_DMA 2 +#define APPLE_SPI_CFG_IE_RXCOMPLETE BIT(7) +#define APPLE_SPI_CFG_IE_TXRXTHRESH BIT(8) +#define APPLE_SPI_CFG_LSB_FIRST BIT(13) +#define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15) +#define APPLE_SPI_CFG_WORD_SIZE_8B 0 +#define APPLE_SPI_CFG_WORD_SIZE_16B 1 +#define APPLE_SPI_CFG_WORD_SIZE_32B 2 +#define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17) +#define APPLE_SPI_CFG_FIFO_THRESH_8B 0 +#define APPLE_SPI_CFG_FIFO_THRESH_4B 1 +#define APPLE_SPI_CFG_FIFO_THRESH_1B 2 +#define APPLE_SPI_CFG_IE_TXCOMPLETE BIT(21) + +#define APPLE_SPI_STATUS 0x008 +#define APPLE_SPI_STATUS_RXCOMPLETE BIT(0) +#define APPLE_SPI_STATUS_TXRXTHRESH BIT(1) +#define APPLE_SPI_STATUS_TXCOMPLETE BIT(2) + +#define APPLE_SPI_PIN 0x00c +#define APPLE_SPI_PIN_KEEP_MOSI BIT(0) +#define APPLE_SPI_PIN_CS BIT(1) + +#define APPLE_SPI_TXDATA 0x010 +#define APPLE_SPI_RXDATA 0x020 +#define APPLE_SPI_CLKDIV 0x030 +#define APPLE_SPI_CLKDIV_MIN 0x002 +#define APPLE_SPI_CLKDIV_MAX 0x7ff +#define APPLE_SPI_RXCNT 0x034 +#define APPLE_SPI_WORD_DELAY 0x038 +#define APPLE_SPI_TXCNT 0x04c + +#define APPLE_SPI_FIFOSTAT 0x10c +#define APPLE_SPI_FIFOSTAT_TXFULL BIT(4) +#define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8) +#define APPLE_SPI_FIFOSTAT_RXEMPTY BIT(20) +#define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24) + +#define APPLE_SPI_IE_XFER 0x130 +#define APPLE_SPI_IF_XFER 0x134 +#define APPLE_SPI_XFER_RXCOMPLETE BIT(0) +#define APPLE_SPI_XFER_TXCOMPLETE BIT(1) + +#define APPLE_SPI_IE_FIFO 0x138 +#define APPLE_SPI_IF_FIFO 0x13c +#define APPLE_SPI_FIFO_RXTHRESH BIT(4) +#define APPLE_SPI_FIFO_TXTHRESH BIT(5) +#define APPLE_SPI_FIFO_RXFULL BIT(8) +#define APPLE_SPI_FIFO_TXEMPTY BIT(9) +#define APPLE_SPI_FIFO_RXUNDERRUN BIT(16) +#define APPLE_SPI_FIFO_TXOVERFLOW BIT(17) + +#define APPLE_SPI_SHIFTCFG 0x150 +#define APPLE_SPI_SHIFTCFG_CLK_ENABLE BIT(0) +#define APPLE_SPI_SHIFTCFG_CS_ENABLE BIT(1) +#define APPLE_SPI_SHIFTCFG_AND_CLK_DATA BIT(8) +#define APPLE_SPI_SHIFTCFG_CS_AS_DATA BIT(9) +#define APPLE_SPI_SHIFTCFG_TX_ENABLE BIT(10) +#define APPLE_SPI_SHIFTCFG_RX_ENABLE BIT(11) +#define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16) +#define APPLE_SPI_SHIFTCFG_OVERRIDE_CS BIT(24) + +#define APPLE_SPI_PINCFG 0x154 +#define APPLE_SPI_PINCFG_KEEP_CLK BIT(0) +#define APPLE_SPI_PINCFG_KEEP_CS BIT(1) +#define APPLE_SPI_PINCFG_KEEP_MOSI BIT(2) +#define APPLE_SPI_PINCFG_CLK_IDLE_VAL BIT(8) +#define APPLE_SPI_PINCFG_CS_IDLE_VAL BIT(9) +#define APPLE_SPI_PINCFG_MOSI_IDLE_VAL BIT(10) + +#define APPLE_SPI_DELAY_PRE 0x160 +#define APPLE_SPI_DELAY_POST 0x168 +#define APPLE_SPI_DELAY_ENABLE BIT(0) +#define APPLE_SPI_DELAY_NO_INTERBYTE BIT(1) +#define APPLE_SPI_DELAY_SET_SCK BIT(4) +#define APPLE_SPI_DELAY_SET_MOSI BIT(6) +#define APPLE_SPI_DELAY_SCK_VAL BIT(8) +#define APPLE_SPI_DELAY_MOSI_VAL BIT(12) + +#define APPLE_SPI_FIFO_DEPTH 16 + +#define APPLE_SPI_TIMEOUT_MS 200 + +struct apple_spi_priv { + void *base; + u32 clkfreq; /* Input clock frequency */ +}; + +static void apple_spi_set_cs(struct apple_spi_priv *priv, int on) +{ + writel(on ? 0 : APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN); +} + +/* Fill Tx FIFO. */ +static void apple_spi_tx(struct apple_spi_priv *priv, uint *len, + const void **dout) +{ + const u8 *out = *dout; + u32 data, fifostat; + uint count; + + fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT); + count = APPLE_SPI_FIFO_DEPTH - + FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_TX, fifostat); + while (*len > 0 && count > 0) { + data = out ? *out++ : 0; + writel(data, priv->base + APPLE_SPI_TXDATA); + (*len)--; + count--; + } + + *dout = out; +} + +/* Empty Rx FIFO. */ +static void apple_spi_rx(struct apple_spi_priv *priv, uint *len, + void **din) +{ + u8 *in = *din; + u32 data, fifostat; + uint count; + + fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT); + count = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_RX, fifostat); + while (*len > 0 && count > 0) { + data = readl(priv->base + APPLE_SPI_RXDATA); + if (in) + *in++ = data; + (*len)--; + count--; + } + + *din = in; +} + +static int apple_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct apple_spi_priv *priv = dev_get_priv(dev->parent); + unsigned long start = get_timer(0); + uint txlen, rxlen; + int ret = 0; + + if ((bitlen % 8) != 0) + return -EINVAL; + txlen = rxlen = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + apple_spi_set_cs(priv, 1); + + if (txlen > 0) { + /* Reset FIFOs */ + writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET, + priv->base + APPLE_SPI_CTRL); + + /* Set the transfer length */ + writel(txlen, priv->base + APPLE_SPI_TXCNT); + writel(rxlen, priv->base + APPLE_SPI_RXCNT); + + /* Prime transmit FIFO */ + apple_spi_tx(priv, &txlen, &dout); + + /* Start transfer */ + writel(APPLE_SPI_CTRL_RUN, priv->base + APPLE_SPI_CTRL); + + while ((txlen > 0 || rxlen > 0)) { + apple_spi_rx(priv, &rxlen, &din); + apple_spi_tx(priv, &txlen, &dout); + + if (get_timer(start) > APPLE_SPI_TIMEOUT_MS) { + ret = -ETIMEDOUT; + break; + } + } + + /* Stop transfer. */ + writel(0, priv->base + APPLE_SPI_CTRL); + } + + if (flags & SPI_XFER_END) + apple_spi_set_cs(priv, 0); + + return ret; +} + +static int apple_spi_set_speed(struct udevice *dev, uint speed) +{ + struct apple_spi_priv *priv = dev_get_priv(dev); + u32 div; + + div = DIV_ROUND_UP(priv->clkfreq, speed); + if (div < APPLE_SPI_CLKDIV_MIN) + div = APPLE_SPI_CLKDIV_MIN; + if (div > APPLE_SPI_CLKDIV_MAX) + div = APPLE_SPI_CLKDIV_MAX; + + writel(div, priv->base + APPLE_SPI_CLKDIV); + + return 0; +} + +static int apple_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +struct dm_spi_ops apple_spi_ops = { + .xfer = apple_spi_xfer, + .set_speed = apple_spi_set_speed, + .set_mode = apple_spi_set_mode, +}; + +static int apple_spi_probe(struct udevice *dev) +{ + struct apple_spi_priv *priv = dev_get_priv(dev); + struct clk clkdev; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &clkdev); + if (ret) + return ret; + priv->clkfreq = clk_get_rate(&clkdev); + + /* Set CS high (inactive) and disable override and auto-CS */ + writel(APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN); + writel(readl(priv->base + APPLE_SPI_SHIFTCFG) & ~APPLE_SPI_SHIFTCFG_OVERRIDE_CS, + priv->base + APPLE_SPI_SHIFTCFG); + writel((readl(priv->base + APPLE_SPI_PINCFG) & ~APPLE_SPI_PINCFG_CS_IDLE_VAL) | + APPLE_SPI_PINCFG_KEEP_CS, priv->base + APPLE_SPI_PINCFG); + + /* Reset FIFOs */ + writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET, + priv->base + APPLE_SPI_CTRL); + + /* Configure defaults */ + writel(FIELD_PREP(APPLE_SPI_CFG_MODE, APPLE_SPI_CFG_MODE_IRQ) | + FIELD_PREP(APPLE_SPI_CFG_WORD_SIZE, APPLE_SPI_CFG_WORD_SIZE_8B) | + FIELD_PREP(APPLE_SPI_CFG_FIFO_THRESH, APPLE_SPI_CFG_FIFO_THRESH_8B), + priv->base + APPLE_SPI_CFG); + + return 0; +} + +static const struct udevice_id apple_spi_of_match[] = { + { .compatible = "apple,spi" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_spi) = { + .name = "apple_spi", + .id = UCLASS_SPI, + .of_match = apple_spi_of_match, + .probe = apple_spi_probe, + .priv_auto = sizeof(struct apple_spi_priv), + .ops = &apple_spi_ops, +}; diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 04ce88c9dd..3b4d1fd626 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -47,13 +47,4 @@ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index e12e54fe4f..763cb8db7c 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -47,13 +47,4 @@ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/apple.h b/include/configs/apple.h index 3e5fb495f1..f12e9bdef5 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -5,7 +5,7 @@ /* Environment */ #define ENV_DEVICE_SETTINGS \ - "stdin=serial,usbkbd\0" \ + "stdin=serial,usbkbd,spikbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" @@ -13,6 +13,12 @@ "fdt_addr_r=0x960100000\0" \ "kernel_addr_r=0x960200000\0" +#if CONFIG_IS_ENABLED(CMD_NVME) + #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) +#else + #define BOOT_TARGET_NVME(func) +#endif + #if CONFIG_IS_ENABLED(CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -20,6 +26,7 @@ #endif #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_NVME(func) \ BOOT_TARGET_USB(func) #include <config_distro_bootcmd.h> diff --git a/include/linux/apple-mailbox.h b/include/linux/apple-mailbox.h new file mode 100644 index 0000000000..720fbb7029 --- /dev/null +++ b/include/linux/apple-mailbox.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Apple mailbox message format + * + * Copyright (C) 2021 The Asahi Linux Contributors + */ + +#ifndef _LINUX_APPLE_MAILBOX_H_ +#define _LINUX_APPLE_MAILBOX_H_ + +#include <linux/types.h> + +/* encodes a single 96bit message sent over the single channel */ +struct apple_mbox_msg { + u64 msg0; + u32 msg1; +}; + +#endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6b21e3918d..a6bc234f51 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1822,8 +1822,6 @@ CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE -CONFIG_SYS_RESET_ADDR -CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_RFD CONFIG_SYS_RGMII1_PHY_ADDR CONFIG_SYS_RGMII2_PHY_ADDR |