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| author | Tom Rini <trini@konsulko.com> | 2021-08-25 06:11:49 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-01 00:47:49 +0300 |
| commit | d8ef01e964d6b56d4cce61a6fb3db65026e1cd52 (patch) | |
| tree | 41cbd3048b409aef34b9046246afea9bd1bdf643 /README | |
| parent | ca2b13c8859e1fbaa550405477c695f769626ffb (diff) | |
| download | u-boot-d8ef01e964d6b56d4cce61a6fb3db65026e1cd52.tar.xz | |
Convert CONFIG_RAMBOOT_PBL et al to Kconfig
This converts the following to Kconfig:
CONFIG_RAMBOOT_PBL
CONFIG_SYS_FSL_PBL_PBI
CONFIG_SYS_FSL_PBL_RCW
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 9 |
1 files changed, 0 insertions, 9 deletions
@@ -477,15 +477,6 @@ The following options need to be configured: CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). - CONFIG_SYS_FSL_PBL_PBI - It enables addition of RCW (Power on reset configuration) in built image. - Please refer doc/README.pblimage for more details - - CONFIG_SYS_FSL_PBL_RCW - It adds PBI(pre-boot instructions) commands in u-boot build image. - PBI commands can be used to configure SoC before it starts the execution. - Please refer doc/README.pblimage for more details - CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian |