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| author | Tom Rini <trini@konsulko.com> | 2022-10-29 03:27:10 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-11-10 18:08:55 +0300 |
| commit | 8c778f78340068cebf5484a9f69de1de5d4eb447 (patch) | |
| tree | dbe5b6dd7db245a93dd6eb3ba3243ed6b624fbc5 /arch/Kconfig | |
| parent | 02f5a01441ecd356b73b491c99d635c67b2ba207 (diff) | |
| download | u-boot-8c778f78340068cebf5484a9f69de1de5d4eb447.tar.xz | |
Convert CONFIG_SYS_NONCACHED_MEMORY to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_NONCACHED_MEMORY
To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to
gate if we are going to have noncached_... functions available and then
continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said
cache. We make this new option depend on both the architectures which
implement support and the drivers which make use of it.
Cc: Tom Warren <twarren@nvidia.com>
Cc: Mingming lee <mingming.lee@mediatek.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/Kconfig')
| -rw-r--r-- | arch/Kconfig | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index e3a456a98d..ae39716697 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -438,6 +438,30 @@ config TPL_SKIP_LOWLEVEL_INIT_ONLY normal CP15 init (such as enabling the instruction cache) is still performed. +config SYS_HAS_NONCACHED_MEMORY + bool "Enable reserving a non-cached memory area for drivers" + depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) + help + This is useful for drivers that would otherwise require a lot of + explicit cache maintenance. For some drivers it's also impossible to + properly maintain the cache. For example if the regions that need to + be flushed are not a multiple of the cache-line size, *and* padding + cannot be allocated between the regions to align them (i.e. if the + HW requires a contiguous array of regions, and the size of each + region is not cache-aligned), then a flush of one region may result + in overwriting data that hardware has written to another region in + the same cache-line. This can happen for example in network drivers + where descriptors for buffers are typically smaller than the CPU + cache-line (e.g. 16 bytes vs. 32 or 64 bytes). + +config SYS_NONCACHED_MEMORY + hex "Size in bytes of the non-cached memory area" + depends on SYS_HAS_NONCACHED_MEMORY + default 0x100000 + help + Size of non-cached memory area. This area of memory will be typically + located right below the malloc() area and mapped uncached in the MMU. + source "arch/arc/Kconfig" source "arch/arm/Kconfig" source "arch/m68k/Kconfig" |