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authorAlexey Brodkin <abrodkin@synopsys.com>2016-08-04 09:21:50 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2016-08-05 12:50:25 +0300
commit699c4e592b32f43d4ba2cc0d53848118a77d590a (patch)
tree75bf7dd85f4d5c2d6a744a0229f5cb4482227381 /arch/arc/lib/interrupts.c
parentffffcd15948d9d1081afd6f1215a9850bd9f4bd5 (diff)
downloadu-boot-699c4e592b32f43d4ba2cc0d53848118a77d590a.tar.xz
arc: Update exception & interrupt handling for ARCv2
Initially IVT for ARCv2 was simply copypasted from ARCompact with some selected fixes so basic stuff works. Now we update it with more ARCv2 specific vectors like * Software Interrupt * Division by zero * Data cache consistency error * Misaligned access Also normal interrupts are now implemented properly and extened to all possible 240 items. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/lib/interrupts.c')
-rw-r--r--arch/arc/lib/interrupts.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c
index d7cab3bb40..ee638d506b 100644
--- a/arch/arc/lib/interrupts.c
+++ b/arch/arc/lib/interrupts.c
@@ -141,3 +141,29 @@ void do_extension(struct pt_regs *regs)
printf("Extension instruction exception\n");
bad_mode(regs);
}
+
+#ifdef CONFIG_ISA_ARCV2
+void do_swi(struct pt_regs *regs)
+{
+ printf("Software Interrupt exception\n");
+ bad_mode(regs);
+}
+
+void do_divzero(unsigned long address, struct pt_regs *regs)
+{
+ printf("Division by zero exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_dcerror(struct pt_regs *regs)
+{
+ printf("Data cache consistency error exception\n");
+ bad_mode(regs);
+}
+
+void do_maligned(unsigned long address, struct pt_regs *regs)
+{
+ printf("Misaligned data access exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+#endif