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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-11 08:39:14 +0300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 17:55:36 +0300 |
| commit | 63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5 (patch) | |
| tree | 065b8277ffa5951efbff0a53bdb8a6f797d7b884 /arch/arm/cpu/armv7/ls102xa/Kconfig | |
| parent | 584f316f115df52fd09a6cf699b29dcf824b4da5 (diff) | |
| download | u-boot-63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5.tar.xz | |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index fadfce4f05..90d99e6cc3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_HAS_CCI400 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -49,9 +50,20 @@ config SECURE_BOOT Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. +config SYS_CCI400_OFFSET + hex "Offset for CCI400 base" + depends on SYS_FSL_HAS_CCI400 + default 0x180000 + help + Offset for CCI400 base. + CCI400 base addr = CCSRBAR + CCI400_OFFSET + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_SRDS_1 bool |