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| author | Yuantian Tang <andy.tang@nxp.com> | 2017-12-11 08:12:09 +0300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-01-10 23:28:14 +0300 |
| commit | 1b76f3b8ab70f221e4272026cabe0b60953eb8cf (patch) | |
| tree | d32351506481359acf62bfd4e50dcb2522011280 /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
| parent | fa60abc6e690627ef8441a0ca6fc5cedd0b16374 (diff) | |
| download | u-boot-1b76f3b8ab70f221e4272026cabe0b60953eb8cf.tar.xz | |
armv8: layerscape: sata: refine port register configuration
Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively. Calculate those parameters from port clock frequency.
Overwrite those registers with calculated values to get better OOB
timing.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ae57c0e31d..dc4a437344 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -341,6 +341,8 @@ int sata_init(void) #ifdef CONFIG_SYS_SATA2 ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); #endif @@ -348,6 +350,8 @@ int sata_init(void) #ifdef CONFIG_SYS_SATA1 ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); @@ -368,6 +372,8 @@ int sata_init(void) /* Disable SATA ECC */ out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); |