diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2020-06-25 17:23:53 +0300 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 11:46:28 +0300 |
| commit | c5f8943965b052d48ef0b66cc860b4627ac7391c (patch) | |
| tree | 64b11bf4df60c58a44d8c2e25e93053ac6c8cd4a /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
| parent | 10669ed96576f367af57bb4200327b9dfed2b44b (diff) | |
| download | u-boot-c5f8943965b052d48ef0b66cc860b4627ac7391c.tar.xz | |
arm64: ls1043a: Remove the workaround of erratum A-009929
The workaround has been implemented in PBI phase, so remove
the duplicated implementation from U-Boot.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ad7ea05935..0cd8e92e81 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -445,20 +445,6 @@ int get_core_volt_from_fuse(void) } #elif defined(CONFIG_FSL_LSCH2) - -static void erratum_a009929(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A009929 - struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; - u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; - u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); - - rstrqmr1 |= 0x00000400; - gur_out32(&gur->rstrqmr1, rstrqmr1); - writel(0x01000000, dcsr_cop_ccp); -#endif -} - /* * This erratum requires setting a value to eddrtqcr1 to optimal * the DDR performance. The eddrtqcr1 register is in SCFG space @@ -724,7 +710,6 @@ void fsl_lsch2_early_init_f(void) #endif /* Erratum */ erratum_a008850_early(); /* part 1 of 2 */ - erratum_a009929(); erratum_a009660(); erratum_a010539(); erratum_a009008(); |