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authorTom Rini <trini@konsulko.com>2017-04-18 18:36:06 +0300
committerTom Rini <trini@konsulko.com>2017-04-18 18:36:06 +0300
commit3c476d841daa491f87c8f07851038afbdf4d90a8 (patch)
tree131891877d7b9b112ebc8c05ab88d53b9b18b702 /arch/arm/cpu/armv8/fsl-layerscape/spl.c
parent9481f186d0bb06e492f62144cacdb5a8367e3cd2 (diff)
parente0dfec863e2ca5088dd797a5b6853d4c0df9002c (diff)
downloadu-boot-3c476d841daa491f87c8f07851038afbdf4d90a8.tar.xz
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/spl.c')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/spl.c20
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 73a8680741..eb730e84a4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -41,13 +41,31 @@ u32 spl_boot_mode(const u32 boot_device)
}
#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
+ /*
+ * In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+#endif
+}
+
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
board_early_init_f();
timer_init();
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
env_init();
#endif
get_clocks();