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authorXiaowei Bao <xiaowei.bao@nxp.com>2019-05-21 13:28:31 +0300
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-06-19 10:24:56 +0300
commit36f50b75238ee5a2589763797bc5b5551e4e8ec2 (patch)
treeeb6359d6cb893d2302bc7ddf586c0a24663a6f5b /arch/arm/cpu
parent123fbbbe84e06f3ff0a8e263275a55ad1e83e380 (diff)
downloadu-boot-36f50b75238ee5a2589763797bc5b5551e4e8ec2.tar.xz
armv8: ls1028a: Add other serdes protocal support
Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
index ef598c4cba..5835a3a69e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
@@ -22,6 +22,19 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
{0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
+ {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
+ {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
+ {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
+ {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
+ {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
+ {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
+ {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
+ {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
+ {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
+ {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
+ {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
+ {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
{}
};