summaryrefslogtreecommitdiff
path: root/arch/arm/cpu
diff options
context:
space:
mode:
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2020-08-06 09:38:19 +0300
committerPriyanka Jain <priyanka.jain@nxp.com>2020-09-24 18:27:32 +0300
commitaf288cb291da3abef6be0875527729296f7de7a0 (patch)
tree8b5468c222ebf6ccc0dee0cd660c5ba5d2a00e5d /arch/arm/cpu
parent223c19076f8b6808ffcb3772dd91d890d180cd65 (diff)
downloadu-boot-af288cb291da3abef6be0875527729296f7de7a0.tar.xz
arm64: Layerscape: Survive LPI one-way reset workaround
The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 5254cdf366..87fb321c63 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -45,7 +45,22 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_GIC_V3_ITS
int ls_gic_rd_tables_init(void *blob)
{
- int ret;
+ struct fdt_memory lpi_base;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int offset, ret;
+
+ offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
+ 0, &size, false);
+
+ lpi_base.start = addr;
+ lpi_base.end = addr + size - 1;
+ ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL);
+ if (ret) {
+ debug("%s: failed to add reserved memory\n", __func__);
+ return ret;
+ }
ret = gic_lpi_tables_init();
if (ret)