diff options
| author | Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> | 2020-07-15 20:18:56 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-29 17:13:40 +0300 |
| commit | 5d9302d478813f6bdd79393eedde76dcf512f403 (patch) | |
| tree | ca55a5c176bbe1f1f9a4d4c3e76cb1d8bdafa8f4 /arch/arm/cpu | |
| parent | 291635aecf84442876030972fd05b767e738f6fb (diff) | |
| download | u-boot-5d9302d478813f6bdd79393eedde76dcf512f403.tar.xz | |
arm: cpu: armv8: add L3 memory flush support
Add L3 memory flush support for NS3.
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/bcmns3/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/bcmns3/lowlevel.S | 89 |
3 files changed, 95 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 2e48df0eb9..7e33a183d5 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile new file mode 100644 index 0000000000..a35e29d11a --- /dev/null +++ b/arch/arm/cpu/armv8/bcmns3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Broadcom. + +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S new file mode 100644 index 0000000000..6709c9a188 --- /dev/null +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#include <asm/macro.h> +#include <linux/linkage.h> + +hnf_pstate_poll: + /* x0 has the desired status, return 0 for success, 1 for timeout + * clobber x1, x2, x3, x4, x6, x7 + */ + mov x1, x0 + mov x7, #0 /* flag for timeout */ + mrs x3, cntpct_el0 /* read timer */ + mov w0, #600 + mov w6, #1000 + mul w0, w0, w6 + add x3, x3, x0 /* timeout after 100 microseconds */ + mov x0, #0x18 + movk x0, #0x6120, lsl #16 /* HNF0_PSTATE_STATUS */ + mov w6, #4 /* HN-F node count */ +1: + ldr x2, [x0] + cmp x2, x1 /* check status */ + b.eq 2f + mrs x4, cntpct_el0 + cmp x4, x3 + b.ls 1b + mov x7, #1 /* timeout */ + b 3f +2: + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b +3: + mov x0, x7 + ret + +hnf_set_pstate: + /* x0 has the desired state, clobber x1, x2, x6 */ + mov x1, x0 + /* power state to SFONLY */ + mov w6, #4 /* HN-F node count */ + mov x0, #0x10 + movk x0, #0x6120, lsl #16 /* HNF0_PSTATE_REQ */ +1: /* set pstate to sfonly */ + ldr x2, [x0] + and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */ + orr x2, x2, x1 + str x2, [x0] + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b + + ret + +ENTRY(__asm_flush_l3_dcache) + /* + * Return status in x0 + * success 0 + * timeout 1 for setting SFONLY, 2 for FAM, 3 for both + */ + mov x29, lr + mov x8, #0 + + dsb sy + mov x0, #0x1 /* HNFPSTAT_SFONLY */ + bl hnf_set_pstate + + mov x0, #0x4 /* SFONLY status */ + bl hnf_pstate_poll + cbz x0, 1f + mov x8, #1 /* timeout */ +1: + dsb sy + mov x0, #0x3 /* HNFPSTAT_FAM */ + bl hnf_set_pstate + + mov x0, #0xc /* FAM status */ + bl hnf_pstate_poll + cbz x0, 1f + add x8, x8, #0x2 +1: + mov x0, x8 + mov lr, x29 + ret +ENDPROC(__asm_flush_l3_dcache) |