diff options
author | Tom Rini <trini@konsulko.com> | 2021-08-28 04:18:30 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-09-01 00:47:49 +0300 |
commit | a2ac2b964bfbb20d6791ee94b9034a50cfadb5b0 (patch) | |
tree | 9ab0cc43b3abf55efbab3014e5a0d818a7c5f051 /arch/arm/cpu | |
parent | ab92b38a0161f0d8efa1c2112d944ef8f755dfbe (diff) | |
download | u-boot-a2ac2b964bfbb20d6791ee94b9034a50cfadb5b0.tar.xz |
Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig
This converts the following to Kconfig:
CONFIG_SKIP_LOWLEVEL_INIT
CONFIG_SKIP_LOWLEVEL_INIT_ONLY
In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/arm1136/start.S | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/start.S | 10 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/start.S | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/start.S | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm946es/start.S | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/start.S | 8 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/cpu/pxa/start.S | 6 | ||||
-rw-r--r-- | arch/arm/cpu/sa1100/start.S | 4 |
10 files changed, 36 insertions, 30 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index da7278e59f..4bc27f6373 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -39,7 +39,7 @@ reset: msr cpsr,r0 /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -62,7 +62,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -81,7 +81,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Jump to board specific initialization... The Mask ROM will have already initialized * basic memory. Go here to bump up clock rate and handle wake up conditions. @@ -91,4 +91,4 @@ cpu_init_crit: mov lr, ip /* restore link */ #endif mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index ecb4e44fd8..9ad1f03142 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -37,8 +37,8 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif @@ -62,8 +62,8 @@ c_runtime_cpu_setup: ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) cpu_init_crit: mov ip, lr @@ -76,4 +76,4 @@ cpu_init_crit: mov lr, ip mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e2b5f2bff4..02cbda9d22 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -53,7 +53,7 @@ copyex: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -78,7 +78,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -97,7 +97,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will @@ -109,4 +109,4 @@ cpu_init_crit: mov lr, ip #endif mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index ff592ba810..0afcc47aad 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -46,7 +46,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -69,7 +69,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush D cache before disabling it @@ -100,7 +100,7 @@ flush_dcache: #endif mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Go setup Memory and board specific bits prior to relocation. */ @@ -109,4 +109,4 @@ flush_dcache: mov lr, r4 /* restore link */ #endif mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 0ec340b1a6..2d5186774a 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -45,7 +45,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -70,7 +70,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -89,7 +89,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Go setup Memory and board specific bits prior to relocation. */ diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0e83e394d5..bfbd85ae64 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index dcb4195d7b..87329d26e1 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -80,11 +80,11 @@ switch_to_hypervisor_ret: #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #ifdef CONFIG_CPU_V7A bl cpu_init_cp15 #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif #endif @@ -320,8 +320,8 @@ skip_errata_801819: mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /************************************************************************* * * CPU_init_critical registers diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9ca61b3f59..b10b56d2d3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1012A select FSL_LAYERSCAPE select FSL_LSCH2 select GICV2 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE @@ -62,6 +63,7 @@ config ARCH_LS1043A select FSL_LSCH2 select GICV2 select HAS_FSL_XHCI_USB if USB_HOST + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -96,6 +98,7 @@ config ARCH_LS1046A select FSL_LSCH2 select GICV2 select HAS_FSL_XHCI_USB if USB_HOST + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -134,6 +137,7 @@ config ARCH_LS1088A select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -181,6 +185,7 @@ config ARCH_LS2080A select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -296,6 +301,7 @@ config ARCH_LX2160A config FSL_LSCH2 bool + select SKIP_LOWLEVEL_INIT select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 575abac09c..896e05f1fd 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -45,7 +45,7 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -92,7 +92,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) cpu_init_crit: /* * flush v4 I/D caches @@ -111,7 +111,7 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */ /* * Enable MMU to use DCache as DRAM. diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 8eb005309e..2f84f20575 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -39,7 +39,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -95,7 +95,7 @@ cpu_init_crit: ldr r1, cpuspeed str r1, [r0, #PPCR] -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will |