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authorSean Anderson <sean.anderson@seco.com>2022-03-23 00:17:35 +0300
committerTom Rini <trini@konsulko.com>2022-04-01 23:56:53 +0300
commite97ac4780d69c719b81086bba615c8568afd14a1 (patch)
tree6003aaab580f6181b363d20eb8c7c32bd1adabd7 /arch/arm/cpu
parent93c3d329707e0d8dc98e5f86938bbedbe15b5349 (diff)
downloadu-boot-e97ac4780d69c719b81086bba615c8568afd14a1.tar.xz
arm64: Save esr in pt_regs
To avoid passing around an extra register everywhere, save esr in pt_regs like the rest. For proper alignment we need to have a second (unused) register. All the printfs have to be adjusted, since it's now an unsigned long and not an int. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/exceptions.S6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
index a15af72e02..001913f429 100644
--- a/arch/arm/cpu/armv8/exceptions.S
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -84,7 +84,8 @@ _save_el_regs:
1: mrs x1, esr_el1
mrs x2, elr_el1
0:
- stp x2, x0, [sp, #-16]!
+ stp x1, x0, [sp, #-16]!
+ stp xzr, x2, [sp, #-16]!
mov x0, sp
ret
@@ -98,7 +99,7 @@ _save_el_regs:
* This is the first part of the shared routine called into from all entries.
*/
exception_exit:
- ldp x2, x0, [sp],#16
+ ldp xzr, x2, [sp],#16
switch_el x11, 3f, 2f, 1f
3: msr elr_el3, x2
b _restore_regs
@@ -118,6 +119,7 @@ exception_exit:
* This is the second part of the shared routine called into from all entries.
*/
_restore_regs:
+ ldp xzr, x0, [sp],#16
ldp x1, x2, [sp],#16
ldp x3, x4, [sp],#16
ldp x5, x6, [sp],#16