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| author | Pierre-Clément Tosi <ptosi@google.com> | 2021-08-27 19:04:10 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-23 15:55:06 +0300 |
| commit | 37479e65a353d6d5328092c092c8dc7dbcd4d001 (patch) | |
| tree | 6fcc08d95f57b7523b77b701e892a6e2ec86b12f /arch/arm/cpu | |
| parent | f050bfacc54deda3598a99645ec90727742494eb (diff) | |
| download | u-boot-37479e65a353d6d5328092c092c8dc7dbcd4d001.tar.xz | |
armv8/cache.S: Triple with single instruction
Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.
Fix the comment as the tripled cache level is placed in x12, not x0.
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/cache.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index eec2958107..d1cee23437 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -80,8 +80,7 @@ ENTRY(__asm_dcache_all) /* x15 <- return address */ loop_level: - lsl x12, x0, #1 - add x12, x12, x0 /* x0 <- tripled cache level */ + add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */ lsr x12, x10, x12 and x12, x12, #7 /* x12 <- cache type */ cmp x12, #2 |