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| author | Patrice Chotard <patrice.chotard@foss.st.com> | 2021-07-19 12:21:51 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-07-29 02:30:22 +0300 |
| commit | 268f6ac1f95c1734e7eea369e93062e52c4aa04a (patch) | |
| tree | 0ec302db5e1a97b04eb51f5cabbc174380488181 /arch/arm/cpu | |
| parent | 558e699d156ebe7f0b51e05a2e38f35fbaa78b0f (diff) | |
| download | u-boot-268f6ac1f95c1734e7eea369e93062e52c4aa04a.tar.xz | |
arm64: Update memcpy_{from, to}io() helpers
At early U-Boot stage, before relocation, MMU is not yet configured
and disabled. DDR may not be configured with the correct memory
attributes (can be configured in MT_DEVICE instead of MT_MEMORY).
In this case, usage of memcpy_{from, to}io() may leads to synchronous
abort in AARCH64 in case the normal memory address is not 64Bits aligned.
To avoid such situation, forbid usage of normal memory cast to (u64 *) in
case MMU is not enabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: mark.kettenis@xs4all.nl
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 15cecb5e0b..3de18c7675 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -719,6 +719,11 @@ int icache_status(void) return (get_sctlr() & CR_I) != 0; } +int mmu_status(void) +{ + return (get_sctlr() & CR_M) != 0; +} + void invalidate_icache_all(void) { __asm_invalidate_icache_all(); @@ -740,6 +745,11 @@ int icache_status(void) return 0; } +int mmu_status(void) +{ + return 0; +} + void invalidate_icache_all(void) { } |