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authorTom Rini <trini@konsulko.com>2021-01-06 00:20:26 +0300
committerTom Rini <trini@konsulko.com>2021-01-06 00:20:26 +0300
commit720620e6916ba40b9a173bb07706d2c73f3c23e7 (patch)
treeb085821f1d1137d80e9bb73f405ea0680db338b9 /arch/arm/dts/fsl-ls1028a.dtsi
parentc86b18074c9d40bfa63cda1068b6dfb810d4377d (diff)
parent62b07b5173e3d04fabfac42cf1f4779d021f94ad (diff)
downloadu-boot-720620e6916ba40b9a173bb07706d2c73f3c23e7.tar.xz
Merge tag 'v2021.01-rc5' into next
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/fsl-ls1028a.dtsi')
-rw-r--r--arch/arm/dts/fsl-ls1028a.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index bf6373d5ec..d0850237c7 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP ls1028a SOC common device tree source
*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*
*/
@@ -91,7 +91,7 @@
status = "disabled";
};
- pcie@3400000 {
+ pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000
0x00 0x03480000 0x0 0x40000 /* lut registers */
@@ -107,7 +107,7 @@
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
- pcie@3500000 {
+ pcie2: pcie@3500000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000
0x00 0x03580000 0x0 0x40000 /* lut registers */