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author | Tom Rini <trini@konsulko.com> | 2021-01-06 00:20:26 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-01-06 00:20:26 +0300 |
commit | 720620e6916ba40b9a173bb07706d2c73f3c23e7 (patch) | |
tree | b085821f1d1137d80e9bb73f405ea0680db338b9 /arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | |
parent | c86b18074c9d40bfa63cda1068b6dfb810d4377d (diff) | |
parent | 62b07b5173e3d04fabfac42cf1f4779d021f94ad (diff) | |
download | u-boot-720620e6916ba40b9a173bb07706d2c73f3c23e7.tar.xz |
Merge tag 'v2021.01-rc5' into next
Prepare v2021.01-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi')
-rw-r--r-- | arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi new file mode 100644 index 0000000000..8e11b0680a --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; |