diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2019-07-11 09:26:24 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-07-18 18:31:30 +0300 |
| commit | 58067b0de1e5d8a07ccb8c3a5497beaa0e043c6b (patch) | |
| tree | dd5cf04d59d4916bf4867b6c13b53037ae201734 /arch/arm/dts/mt7629.dtsi | |
| parent | 1b96da67a0f5c70e4096bec9ce0769925f70513f (diff) | |
| download | u-boot-58067b0de1e5d8a07ccb8c3a5497beaa0e043c6b.tar.xz | |
arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi
The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.
This patch reverses these two clocks to solve this issue.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'arch/arm/dts/mt7629.dtsi')
| -rw-r--r-- | arch/arm/dts/mt7629.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index c87115e0fe..ecbd29d7ae 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -82,8 +82,8 @@ compatible = "mediatek,timer"; reg = <0x10004000 0x80>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_10M_SEL>, - <&topckgen CLK_TOP_CLKXTAL_D4>; + clocks = <&topckgen CLK_TOP_CLKXTAL_D4>, + <&topckgen CLK_TOP_10M_SEL>; clock-names = "mux", "src"; u-boot,dm-pre-reloc; }; |