diff options
author | Hans de Goede <hdegoede@redhat.com> | 2016-03-14 19:37:09 +0300 |
---|---|---|
committer | Hans de Goede <hdegoede@redhat.com> | 2016-03-24 00:04:13 +0300 |
commit | 80e5f83c0fc4bf42110cc55ce671ad7ddc7b08a4 (patch) | |
tree | 39fe4223027504cf9fdfa54c2212401be4a95b92 /arch/arm/dts/sun8i-a83t.dtsi | |
parent | 4bb656e9dde2019cb42ac4c27b3a114a801ad127 (diff) | |
download | u-boot-80e5f83c0fc4bf42110cc55ce671ad7ddc7b08a4.tar.xz |
sunxi: Sync dts files with the upstream kernel
Sync dts files with the upstream kernel including
changes queued for 4.6:
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/commit/?h=sunxi/dt-for-4.6
Note this adds a number of new unused board dts files. I've asked the
authors of the kernel commits adding these to submit a matching defconfig
to u-boot.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/dts/sun8i-a83t.dtsi')
-rw-r--r-- | arch/arm/dts/sun8i-a83t.dtsi | 125 |
1 files changed, 53 insertions, 72 deletions
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi index 245b819d10..d3473f81b1 100644 --- a/arch/arm/dts/sun8i-a83t.dtsi +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -52,12 +52,6 @@ / { interrupt-parent = <&gic>; - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -85,6 +79,7 @@ device_type = "cpu"; reg = <3>; }; + cpu@100 { compatible = "arm,cortex-a7"; device_type = "cpu"; @@ -96,6 +91,7 @@ device_type = "cpu"; reg = <0x101>; }; + cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; @@ -109,18 +105,12 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; clocks { @@ -128,6 +118,7 @@ #size-cells = <1>; ranges; + /* TODO: PRCM block has a mux for this. */ osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -135,36 +126,39 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + /* + * This is called "internal OSC" in some places. + * It is an internal RC-based oscillator. + * TODO: Its controls are in the PRCM block. + */ + osc16M: osc16M_clk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-frequency = <16000000>; + clock-output-names = "osc16M"; + }; + + osc16Md512: osc16Md512_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <512>; + clock-mult = <1>; + clocks = <&osc16M>; + clock-output-names = "osc16M-d512"; }; }; - soc@01c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - pio: pinctrl@01c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c20800 0x400>; clocks = <&osc24M>; gpio-controller; @@ -172,27 +166,6 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PH0", "PH1"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PH2", "PH3"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -201,24 +174,6 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - uart0_pins_a: uart0@0 { allwinner,pins = "PF2", "PF4"; allwinner,function = "uart0"; @@ -234,6 +189,21 @@ }; }; + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -243,5 +213,16 @@ clocks = <&osc24M>; status = "disabled"; }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + }; }; }; |