diff options
| author | Michal Simek <michal.simek@amd.com> | 2022-09-19 15:21:10 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-09-26 15:23:30 +0300 |
| commit | f2641f066b53a2bbb933bccffd696a875fd9adf5 (patch) | |
| tree | 48371cc0b5563b67014893a49342a8af1ec06fc5 /arch/arm/dts/versal-net-mini.dts | |
| parent | ce40cbdf1f839a746996193d42abd6f3e36f07e6 (diff) | |
| download | u-boot-f2641f066b53a2bbb933bccffd696a875fd9adf5.tar.xz | |
arm64: versal-net: Add support for mini configuration
Versal NET mini configuration is designed for running memory test. Current
output is on DCC but changing serial0 alias to pl011 will move console to
serial port.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm/dts/versal-net-mini.dts')
| -rw-r--r-- | arch/arm/dts/versal-net-mini.dts | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts new file mode 100644 index 0000000000..8c29a6ed6b --- /dev/null +++ b/arch/arm/dts/versal-net-mini.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "xlnx,versal-net-mini"; + model = "Xilinx Versal NET MINI"; + #address-cells = <2>; + #size-cells = <2>; + + memory: memory@0 { + reg = <0 0xBBF00000 0 0x100000>, <0 0 0 0x80000000>; + device_type = "memory"; + }; + + aliases { + /* serial0 = &serial0; */ + serial0 = &dcc; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + clk1: clk1 { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: axi { + compatible = "simple-bus"; + u-boot,dm-pre-reloc; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial0: serial@f1920000 { + u-boot,dm-pre-reloc; + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xf1920000 0 0x1000>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + clocks = <&clk1>, <&clk1>; + clock = <1000000>; + current-speed = <115200>; + skip-init; + }; + }; +}; |