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| author | Johan Jonker <jbx6244@gmail.com> | 2023-03-15 21:33:50 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-04-21 10:16:01 +0300 |
| commit | bf13676e0b0cbdc343dce276c20a2fdb5540ab44 (patch) | |
| tree | 7342905b9ed4e8baabf625583a7bb885482c3d47 /arch/arm/dts | |
| parent | e2b57ffbafd044c40491fa4f74b049026cdca116 (diff) | |
| download | u-boot-bf13676e0b0cbdc343dce276c20a2fdb5540ab44.tar.xz | |
arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/rk3288-u-boot.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm/dts/rk3288.dtsi | 17 |
2 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 1894162153..1920698884 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -91,6 +91,11 @@ bootph-all; }; +&edp { + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; +}; + &gpio7 { bootph-all; }; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index f06d1f5bcc..9f92446654 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -1177,19 +1177,24 @@ }; edp: dp@ff970000 { - compatible = "rockchip,rk3288-edp"; + compatible = "rockchip,rk3288-dp"; reg = <0xff970000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; - clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&edp_phy>; + phy-names = "dp"; + power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_EDP>; - reset-names = "edp"; + reset-names = "dp"; rockchip,grf = <&grf>; - power-domains = <&power RK3288_PD_VIO>; status = "disabled"; ports { - edp_in: port { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; edp_in_vopb: endpoint@0 { |