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| author | Michael Walle <michael@walle.cc> | 2020-06-01 22:53:26 +0300 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 11:46:27 +0300 |
| commit | 3d3fe8b12d1973b207ee0406709ff521eec83bf7 (patch) | |
| tree | 99569fc01e92f224208a4563132a762b1957929f /arch/arm/include/asm/arch-fsl-layerscape | |
| parent | ae846a6119dda1553177ff65dad22c2a0494d9fa (diff) | |
| download | u-boot-3d3fe8b12d1973b207ee0406709ff521eec83bf7.tar.xz | |
armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 00aa91b0a2..623977651a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -43,7 +43,6 @@ static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } #endif void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif |