global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

5 files changed, 84 insertions, 84 deletions

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5824778ca2..ff752c21b1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -24,7 +24,7 @@
 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
 #define CONFIG_SYS_PAGE_SIZE		0x10000
 #ifndef L1_CACHE_BYTES
@@ -32,9 +32,9 @@
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
 #endif
 
-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
@@ -95,7 +95,7 @@
 #define EPU_EPGCR		0x700060000ULL
 
 #elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
 #define CONFIG_SYS_PAGE_SIZE		0x10000
 
 #define	SRDS_MAX_LANES	4
@@ -126,9 +126,9 @@
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* LX2160A/LX2162A Soc Support */
 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@@ -139,13 +139,13 @@
 #define L1_CACHE_SHIFT		6
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
 #endif
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
 
 #define CONFIG_SYS_PAGE_SIZE			0x10000
 
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
 
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
@@ -161,7 +161,7 @@
 /* DCFG - GUR */
 
 #elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
 #define CONFIG_FSL_TZASC_400
 
 /* TZ Protection Controller Definitions */
@@ -180,9 +180,9 @@
 #define	SRDS_MAX_LANES	4
 #define	SRDS_BITS_PER_LANE	4
 
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE				0x06000000
@@ -200,9 +200,9 @@
 /* DCFG - GUR */
 
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
 
 #define DCSR_DCFG_SBEESR2			0x20140534
 #define DCSR_DCFG_MBEESR2			0x20140544
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c51b65ea36..4db479140e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -10,7 +10,7 @@
 #ifdef CONFIG_FSL_LSCH3
 #define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
 #define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
+#define CFG_SYS_FSL_QSPI_BASE1	0x20000000
 #define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
@@ -19,7 +19,7 @@
 #endif
 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
+#define CFG_SYS_FSL_QSPI_BASE2	0x400000000
 #define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
@@ -73,7 +73,7 @@
 #define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
 #define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
 #define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
-#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CFG_SYS_FSL_QSPI_BASE	0x40000000
 #define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
 #define CONFIG_SYS_FSL_IFC_BASE		0x60000000
 #define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 8af0d35d27..9cddb41a89 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -70,7 +70,7 @@ void fdt_fixup_icid(void *blob);
 
 #define SET_SCFG_ICID(compat, streamid, name, compataddr) \
 	SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
-		offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+		offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
 		compataddr, SCFG_IS_LE)
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
@@ -83,7 +83,7 @@ void fdt_fixup_icid(void *blob);
 
 #define SET_SDHC_ICID(streamid) \
 	SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
-		CONFIG_SYS_FSL_ESDHC_ADDR)
+		CFG_SYS_FSL_ESDHC_ADDR)
 
 #define SET_EDMA_ICID(streamid) \
 	SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@@ -102,14 +102,14 @@ void fdt_fixup_icid(void *blob);
 #define SET_QMAN_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
 		offsetof(struct ccsr_qman, liodnr) + \
-		CONFIG_SYS_FSL_QMAN_ADDR, \
-		CONFIG_SYS_FSL_QMAN_ADDR, false)
+		CFG_SYS_FSL_QMAN_ADDR, \
+		CFG_SYS_FSL_QMAN_ADDR, false)
 
 #define SET_BMAN_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
 		offsetof(struct ccsr_bman, liodnr) + \
-		CONFIG_SYS_FSL_BMAN_ADDR, \
-		CONFIG_SYS_FSL_BMAN_ADDR, false)
+		CFG_SYS_FSL_BMAN_ADDR, \
+		CFG_SYS_FSL_BMAN_ADDR, false)
 
 #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
 	{ .port_id = (_port_id), .icid = (streamid) }
@@ -119,8 +119,8 @@ void fdt_fixup_icid(void *blob);
 #define SET_SEC_QI_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
 		0, offsetof(ccsr_sec_t, qilcr_ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, \
-		CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+		CFG_SYS_FSL_SEC_ADDR, \
+		CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
 
 extern struct fman_icid_id_table fman_icid_tbl[];
 extern int fman_icid_tbl_sz;
@@ -137,7 +137,7 @@ extern int fman_icid_tbl_sz;
 
 #define SET_GUR_ICID(compat, streamid, name, compataddr) \
 	SET_ICID_ENTRY(compat, streamid, streamid, \
-		offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+		offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
 		compataddr, GUR_IS_LE)
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
@@ -180,24 +180,24 @@ extern int fman_icid_tbl_sz;
 	SET_ICID_ENTRY( \
 		(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
 		(FSL_SEC_JR##jr_num##_OFFSET ==  \
-			SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+			SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
 			? NULL \
 			: "fsl,sec-v4.0-job-ring"), \
 		streamid, \
 		SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, \
+		CFG_SYS_FSL_SEC_ADDR, \
 		FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
 
 #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
 	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+		CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
 
 #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
 	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+		CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
 
 extern struct icid_id_table icid_tbl[];
 extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2b73647ab4..e8bd8d2713 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -14,18 +14,18 @@
 #define CONFIG_SYS_DCSRBAR			0x20000000
 #define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
 
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
-#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
-#define CONFIG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
-#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CFG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
+#define CFG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
+#define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
@@ -65,7 +65,7 @@
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
 
-#define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
+#define CFG_SYS_FSL_TIMER_ADDR		0x02b00000
 
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
@@ -165,24 +165,24 @@ struct sys_info {
 	unsigned long freq_qman;
 };
 
-#define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
+#define CFG_SYS_FSL_FM1_OFFSET		0xa00000
 
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
-#define CONFIG_SYS_FSL_FM1_ADDR			\
-		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
-		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
+#define CFG_SYS_FSL_FM1_ADDR			\
+		(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR		\
+		(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
-#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET		0x700000ull
+#define CFG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define FSL_SEC_JR0_OFFSET			CFG_SYS_FSL_JR0_OFFSET
 #define FSL_SEC_JR1_OFFSET			0x720000ull
 #define FSL_SEC_JR2_OFFSET			0x730000ull
 #define FSL_SEC_JR3_OFFSET			0x740000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 570397b3c0..f1ffb2327d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -9,19 +9,19 @@
 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
 #define __ARCH_FSL_LSCH3_IMMAP_H_
 
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
+#define CFG_SYS_FSL_DDR3_ADDR		0x08210000
+#define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
+#define CFG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
+#define CFG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
 #else
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
+#define CFG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
 #endif
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
+#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
+#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
 #else
@@ -29,8 +29,8 @@
 #define SYS_NXP_FSPI_LUTKEY_BASE_ADDR		0x18
 #define SYS_NXP_FSPI_LUT_BASE_ADDR		0x200
 #endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
-#define FSL_ESDHC1_BASE_ADDR			CONFIG_SYS_FSL_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR			CFG_SYS_FSL_ESDHC_ADDR
 #define FSL_ESDHC2_BASE_ADDR			(CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
@@ -38,20 +38,20 @@
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR	0x023d0000
-#define CONFIG_SYS_FSL_TIMER_ADDR		0x023e0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
+#define CFG_SYS_FSL_TIMER_ADDR		0x023e0000
+#define CFG_SYS_FSL_PMU_CLTBENR		(CFG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
-#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-#define FSL_LSCH3_SVR		(CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR		(CFG_SYS_FSL_GUTS_ADDR + 0xA4)
 
-#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
+#define CFG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
+#define CFG_SYS_FSL_WRIOP1_MDIO1	(CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CFG_SYS_FSL_WRIOP1_MDIO2	(CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CFG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
 
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
+#define CFG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
+#define CFG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
+#define CFG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
 
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
@@ -108,16 +108,16 @@
 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
-#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET		0x07000000ull
+#define CFG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define FSL_SEC_JR0_OFFSET			CFG_SYS_FSL_JR0_OFFSET
 #define FSL_SEC_JR1_OFFSET			0x07020000ull
 #define FSL_SEC_JR2_OFFSET			0x07030000ull
 #define FSL_SEC_JR3_OFFSET			0x07040000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)