diff options
| author | Laurentiu Tudor <laurentiu.tudor@nxp.com> | 2018-08-27 17:33:57 +0300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-09-27 18:56:40 +0300 |
| commit | 6fae6a1fd6bf5001a372701e0764ab0820760d55 (patch) | |
| tree | a717de66d72b5c4853c9685529845d60468f9431 /arch/arm/include/asm/arch-fsl-layerscape | |
| parent | 87519a9ecefaabc707535a0111b745a1189e3b29 (diff) | |
| download | u-boot-6fae6a1fd6bf5001a372701e0764ab0820760d55.tar.xz | |
armv8: fsl-layerscape: add missing qe base address define
Add define for QUICC Engine register block base address.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
[York S: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index be0a6ae363..8c10526a6c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -85,6 +85,8 @@ #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) +#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) |