diff options
| author | Ye Li <ye.li@nxp.com> | 2022-04-06 09:30:13 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-04-12 18:33:56 +0300 |
| commit | 4ab38f6822d9564da7b85649e6bc7d5c9d603350 (patch) | |
| tree | b6d2bf9c03d739267d2b2243a89ce68e0ac7f38c /arch/arm/include/asm/arch-imx8ulp | |
| parent | a092f33305d8f64c30794305746a1807c55f2063 (diff) | |
| download | u-boot-4ab38f6822d9564da7b85649e6bc7d5c9d603350.tar.xz | |
imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-imx8ulp')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8ulp/cgc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h index e45f04624d..83a246b15a 100644 --- a/arch/arm/include/asm/arch-imx8ulp/cgc.h +++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h @@ -150,7 +150,7 @@ void cgc1_pll3_init(ulong freq); void cgc1_pll2_init(ulong freq); void cgc1_soscdiv_init(void); void cgc1_init_core_clk(ulong freq); -void cgc2_pll4_init(void); +void cgc2_pll4_init(bool pll4_reset); void cgc2_ddrclk_config(u32 src, u32 div); void cgc2_ddrclk_wait_unlock(void); u32 cgc1_sosc_div(enum cgc_clk clk); |