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| author | Franck LENORMAND <franck.lenormand@nxp.com> | 2021-03-25 12:30:23 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-04-08 10:18:29 +0300 |
| commit | b5438002416d24e09ddd9ad68dbd1b87548de157 (patch) | |
| tree | e308708d07f144072ab3db397934c96129ce7704 /arch/arm/include/asm/arch-mx7ulp | |
| parent | 68a905d1ff5454201e1617d1cf920aa3648a5855 (diff) | |
| download | u-boot-b5438002416d24e09ddd9ad68dbd1b87548de157.tar.xz | |
caam: enable support for iMX7ULP
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx7ulp')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 9a420dc30b..cb0c2c15c0 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -16,6 +16,8 @@ #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) +#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE + #define OCRAM_0_BASE (0x2F000000) #define OCRAM_0_SIZE (SZ_128K) #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) @@ -224,6 +226,16 @@ #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) +#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */ + +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) |