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authorQuentin Schulz <quentin.schulz@theobroma-systems.com>2022-09-15 13:12:47 +0300
committerKever Yang <kever.yang@rock-chips.com>2022-10-19 14:30:48 +0300
commitd0af506625ff909b123a298e435a95ae1b8ee3e7 (patch)
tree841b006341f93f0758c7679d3181de086fb31923 /arch/arm/include/asm/arch-rockchip
parentd774b2651a3b44fa2b821e1b412732aa6c4d2d45 (diff)
downloadu-boot-d0af506625ff909b123a298e435a95ae1b8ee3e7.tar.xz
rockchip: px30: support debug uart on UART0
UART0 can obviously also be used for debug uart in U-Boot, so let's add its support. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip')
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_px30.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index 732ca37040..b66277fc7f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -445,5 +445,24 @@ enum {
/* CRU_PMU_CLK_SEL0_CON */
CLK_PMU_PCLK_DIV_SHIFT = 0,
CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
+
+ /* CRU_PMU_CLKSEL3_CON */
+ UART0_PLL_SEL_SHIFT = 14,
+ UART0_PLL_SEL_MASK = 3 << UART0_PLL_SEL_SHIFT,
+ UART0_PLL_SEL_GPLL = 0,
+ UART0_PLL_SEL_24M,
+ UART0_PLL_SEL_480M,
+ UART0_PLL_SEL_NPLL,
+ UART0_DIV_CON_SHIFT = 0,
+ UART0_DIV_CON_MASK = 0x1f << UART0_DIV_CON_SHIFT,
+
+ /* CRU_PMU_CLKSEL4_CON */
+ UART0_CLK_SEL_SHIFT = 14,
+ UART0_CLK_SEL_MASK = 3 << UART0_PLL_SEL_SHIFT,
+ UART0_CLK_SEL_UART0 = 0,
+ UART0_CLK_SEL_UART0_NP5,
+ UART0_CLK_SEL_UART0_FRAC,
+ UART0_DIVNP5_SHIFT = 0,
+ UART0_DIVNP5_MASK = 0x1f << UART0_DIVNP5_SHIFT,
};
#endif