diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2020-01-09 11:52:18 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2020-01-30 06:44:01 +0300 |
| commit | ee6321fa14050e54211acd49e8b6890ee15b2518 (patch) | |
| tree | f7036b969955018cd7e84721d5617aa41257cf48 /arch/arm/include/asm/arch-rockchip | |
| parent | b52a199e323e68ff5cbda4feb03731cb0d39587a (diff) | |
| download | u-boot-ee6321fa14050e54211acd49e8b6890ee15b2518.tar.xz | |
rockchip: Add common reset cause
Add cpu reset cause in common cpu-info file.
This would help to print the reset cause for
various resets.
Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 14 |
2 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 475d772fb6..5cf2aec11a 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -13,6 +13,18 @@ # include <asm/arch-rockchip/cru_rk3399.h> #endif +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), + GLB_RST_ST_MASK = GENMASK(5, 0), +}; + #define MHz 1000000 #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index 7aa6efe46c..412b73e55f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -51,7 +51,7 @@ struct rockchip_cru { u32 cru_glb_cnt_th; u32 cru_glb_rst_con; u32 reserved3; - u32 cru_glb_rst_st; + u32 glb_rst_st; u32 reserved4; u32 cru_sdmmc_con[2]; u32 cru_sdio0_con[2]; @@ -227,16 +227,4 @@ enum { CLKF_MASK = 0x1fff << CLKF_SHIFT, }; -/* CRU_GLB_RST_ST */ -enum { - GLB_POR_RST, - FST_GLB_RST_ST = BIT(0), - SND_GLB_RST_ST = BIT(1), - FST_GLB_TSADC_RST_ST = BIT(2), - SND_GLB_TSADC_RST_ST = BIT(3), - FST_GLB_WDT_RST_ST = BIT(4), - SND_GLB_WDT_RST_ST = BIT(5), - GLB_RST_ST_MASK = GENMASK(5, 0), -}; - #endif |