diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2022-01-29 18:23:04 +0300 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-02-04 03:09:57 +0300 |
| commit | 645ee3c25d74db85c19a75e6ce6debe52f8c2119 (patch) | |
| tree | f16e8b52cddaab0ee50818b2c7ad39bfa1cf7b3f /arch/arm/include/asm/arch-sunxi | |
| parent | 5d35f0f254cde3d8830a88193e143cd204785643 (diff) | |
| download | u-boot-645ee3c25d74db85c19a75e6ce6debe52f8c2119.tar.xz | |
sunxi: Add F1C100s DRAM initial support
Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_suniv.h | 46 |
2 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index c3b3e1f512..682daae6b1 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -31,6 +31,8 @@ #include <asm/arch/dram_sun50i_h6.h> #elif defined(CONFIG_MACH_SUN50I_H616) #include <asm/arch/dram_sun50i_h616.h> +#elif defined(CONFIG_MACH_SUNIV) +#include <asm/arch/dram_suniv.h> #else #include <asm/arch/dram_sun4i.h> #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_suniv.h b/arch/arm/include/asm/arch-sunxi/dram_suniv.h new file mode 100644 index 0000000000..6f4c0512d6 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_suniv.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * suniv DRAM controller register definition + * + * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io> + * + * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is: + * + * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com> + */ + +#define PIO_SDRAM_DRV (0x2c0) +#define PIO_SDRAM_PULL (0x2c4) + +#define DRAM_SCONR (0x00) +#define DRAM_STMG0R (0x04) +#define DRAM_STMG1R (0x08) +#define DRAM_SCTLR (0x0c) +#define DRAM_SREFR (0x10) +#define DRAM_SEXTMR (0x14) +#define DRAM_DDLYR (0x24) +#define DRAM_DADRR (0x28) +#define DRAM_DVALR (0x2c) +#define DRAM_DRPTR0 (0x30) +#define DRAM_DRPTR1 (0x34) +#define DRAM_DRPTR2 (0x38) +#define DRAM_DRPTR3 (0x3c) +#define DRAM_SEFR (0x40) +#define DRAM_MAE (0x44) +#define DRAM_ASPR (0x48) +#define DRAM_SDLY0 (0x4C) +#define DRAM_SDLY1 (0x50) +#define DRAM_SDLY2 (0x54) +#define DRAM_MCR0 (0x100) +#define DRAM_MCR1 (0x104) +#define DRAM_MCR2 (0x108) +#define DRAM_MCR3 (0x10c) +#define DRAM_MCR4 (0x110) +#define DRAM_MCR5 (0x114) +#define DRAM_MCR6 (0x118) +#define DRAM_MCR7 (0x11c) +#define DRAM_MCR8 (0x120) +#define DRAM_MCR9 (0x124) +#define DRAM_MCR10 (0x128) +#define DRAM_MCR11 (0x12c) +#define DRAM_BWCR (0x140) |