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authorPeng Fan <peng.fan@nxp.com>2018-10-18 15:28:17 +0300
committerStefano Babic <sbabic@denx.de>2018-10-22 13:59:01 +0300
commitfa64d8429b525f7db2e22ed67d1d3c682e89078c (patch)
tree71e50d9a4d14e10545240b1d8f621444fd5480a9 /arch/arm/include/asm/armv8
parent5710a48afc0fbc5a90727404f1da1df52af99c46 (diff)
downloadu-boot-fa64d8429b525f7db2e22ed67d1d3c682e89078c.tar.xz
armv8: add cpu core helper functions
Add helper functions to identify different armv8 variants. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/armv8')
-rw-r--r--arch/arm/include/asm/armv8/cpu.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
new file mode 100644
index 0000000000..40d54dc85a
--- /dev/null
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define MIDR_PARTNUM_CORTEX_A35 0xD04
+#define MIDR_PARTNUM_CORTEX_A53 0xD03
+#define MIDR_PARTNUM_CORTEX_A72 0xD08
+#define MIDR_PARTNUM_SHIFT 0x4
+#define MIDR_PARTNUM_MASK (0xFFF << 0x4)
+
+static inline unsigned int read_midr(void)
+{
+ unsigned long val;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (val));
+
+ return val;
+}
+
+#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+ MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
+#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+ MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
+#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
+ MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)