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authorSimon Glass <sjg@chromium.org>2017-04-06 02:53:18 +0300
committerTom Rini <trini@konsulko.com>2017-05-12 05:03:39 +0300
commit6775a8208e3ac60f09b982c2d7b3258e0af86540 (patch)
tree0769a9a7530e304cd65a5f661458d9036b788c67 /arch/arm/include/asm/system.h
parentf97cae95759efd4dbb19acdde201a1f13815832a (diff)
downloadu-boot-6775a8208e3ac60f09b982c2d7b3258e0af86540.tar.xz
arm: Support cache invalidate
At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/system.h')
-rw-r--r--arch/arm/include/asm/system.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9c3261c884..79bd19af7d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -180,6 +180,21 @@ static inline unsigned long read_mpidr(void)
void __asm_flush_dcache_all(void);
void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
+
+/**
+ * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
+ *
+ * This performance an invalidate from @start to @end - 1. Both addresses
+ * should be cache-aligned, otherwise this function will align the start
+ * address and may continue past the end address.
+ *
+ * Data in the address range is evicted from the cache and is not written back
+ * to memory.
+ *
+ * @start: Start address to invalidate
+ * @end: End address to invalidate up to (exclusive)
+ */
+void __asm_invalidate_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
int __asm_invalidate_l3_dcache(void);